NXP Semiconductors LPC55S6 Series Application Note
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NXP Semiconductors LPC55S6 Series Application Note

Gpio and usage
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AN12326
LPC55S6x Secure GPIO and Usage
Rev. 0 - 15 January 2019

1 Background

LPC55S6x has Secure GPIO module whose usage is closely related to normal
GPIO, TrustZone, and Secure AHB Controller. This section briefly introduces
these functions. For more information, refer to LPC55S6x User Manual.
1.1 TrustZone and Secure AHB Controller
1.1.1 TrustZone
TrustZone for Armv8-M are available on all LPC55S6x devices to protect
secure resources from malicious code. Such secure resources may include
secure memory blocks (code/data), and secure peripherals. It is achieved by
segmentation of address space into either Secure (S) or Non-secure (NS).
TrustZone can filter address access from CPU0 based on specific security
attribute (S, NS) assigned to that address space.
As shown in
Fig
1, CM33 CPU in Secure state (CPU-S) can execute
instructions from Secure memory (S-memory), but not allowed to execute
instructions directly from Non-secure memory (NS-memory). However, CPU-
S can access data in both S-memory and NS-memory. CPU-NS can execute
instructions only from NS-memory, and not allowed to execute instructions from
S-memory. CPU-NS can access data only in NS-memory, but not allowed to access data from S-memory.
Contents
1 Background.......................................... 1
1.1 TrustZone and Secure
AHB Controller........................ 1
1.2 Normal GPIO...........................3
and Secure PINT................................4
2.1 Secure GPIO Mask................. 6
2.2 Secure GPIO...........................6
2.3 Secure PINT........................... 6
3 Usage.................................................... 6
4 Example................................................ 9
4.1 Environment............................9
4.2 Steps and result...................... 9
5 Conclusion..........................................11
6 Revision history................................. 11
Application Note

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Summary of Contents for NXP Semiconductors LPC55S6 Series

  • Page 1: Table Of Contents

    AN12326 LPC55S6x Secure GPIO and Usage Rev. 0 — 15 January 2019 Application Note Contents 1 Background 1 Background.......... 1 1.1 TrustZone and Secure LPC55S6x has Secure GPIO module whose usage is closely related to normal AHB Controller......1 GPIO, TrustZone, and Secure AHB Controller. This section briefly introduces 1.2 Normal GPIO......3 these functions.
  • Page 2 NXP Semiconductors Background Figure 1. Secure state and Non-secure state view for TrustZone In summary: • NS application code “trust” that secure code, does not corrupt/modify NS code or data inadvertently or on purpose to create malfunction or hazard • S application code does not “trust” NS application code and disallows access to a CPU-NS 1.1.2 Secure AHB Controller...

  • Page 3: Normal Gpio

    NXP Semiconductors Background Figure 2. Secure-state and Non-secure state view for TrustZone and Secure AHB Controller 1.2 Normal GPIO Normal GPIO is the most common digital peripheral in a microcontroller. Normal GPIO of LPC MCU is very flexible and powerful.

  • Page 4: Secure Gpio, Secure Gpio Mask And Secure Pint

    NXP Semiconductors Secure GPIO, Secure GPIO Mask and Secure PINT Figure 3. Normal GPIO 2 Secure GPIO, Secure GPIO Mask and Secure PINT Due to the architecture of normal GPIO, all digital IO pins states are readable through normal GPIO module from the GPIO read path, independent of which function is chosen for this pin as aforementioned.
  • Page 5 NXP Semiconductors Secure GPIO, Secure GPIO Mask and Secure PINT In addition, if Secure-world need operate GPIO, it cannot use normal GPIO as normal GPIO is masked. In this case, a new module, named Secure GPIO is introduced on LPC55S6x. Unlike normal GPIO, this Secure GPIO functionality is available only if FUNC=10 in IOCON.

  • Page 6: Secure Gpio Mask

    NXP Semiconductors Usage 2.1 Secure GPIO Mask Each GPIO has a Secure GPIO MASK. As shown in Fig 4 , we can think of the Secure GPIO Mask as one input of the AND gate. Its default value is 1. Through Secure GPIO Mask, we can control the on/off state of the normal GPIO read path.

  • Page 7: Set One Io To Secure Gpio

    NXP Semiconductors Usage Figure 5. Usage of SEC_GPIO_MASK The following code snippet shows how to mask P0_5 pin by using Secure GPIO MASK: Figure 6. Set the SEC_GPIO_MASK of P0_5 to 0 3.2 Set one IO to Secure GPIO Following are the steps to configure an I/O pin to Secure pin: –...

  • Page 8: Usage Of Secure Pint

    NXP Semiconductors Usage – Make the Secure GPIO IP Secure: Figure 8. Make the Secure GPIO IP Secure – Make the IOCON block Secure: Figure 9. Make the IOCON block Secure – Configure P0_5 pin function to Secure GPIO (FUNC=10): Figure 10.

  • Page 9: Example

    NXP Semiconductors Example Figure 12. Make the Secure PINT register Secure 4 Example 4.1 Environment 4.1.1 Hardware environment • Board — LPCXpresso55S69(LPC55S69-EVK Revision 2) • Debugger — Integrated CMSIS-DAP debugger on the board • Miscellaneous — 1 Micro USB cable —...
  • Page 10 NXP Semiconductors Example Figure 13. Location of the demo project There are two projects in the workspace. Figure 14. Demo projects • Configure “secure_gpio_s” and “secure_gpio_ns” projects as shown below: Figure 15. Configuration of the projects 2. Compile & Download •...

  • Page 11: Conclusion

    NXP Semiconductors Conclusion • Connect the micro USB cable between PC and P6 link on the board while pressing and holding down ISP button. • Download compiled executable file. • Release ISP button after the download is successful. 3. Run Reset the board to run by pressing the Reset (S4) button on the board.
  • Page 12 How To Reach Us Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to Home Page: design or fabricate any integrated circuits based on the information in this document. NXP nxp.com reserves the right to make changes without further notice to any products herein.

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