Texas Instruments TMS320C64X Programmer's Reference Manual page 51

Implementation Notes
Benchmarks
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Bank Conflicts: No bank conflicts occur.
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Interruptibility: The code is interruptible.
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The routine uses log
either a radix-2 or radix-4 transform on the last stage depending on nx. If
nx is a power of 4, then this last stage is also a radix-4 transform, otherwise
it is a radix-2 transform.
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A special sequence of coefficients used as generated above produces the
FFT. This collapses the inner 2 loops in the traditional Burrus and Parks
implementation.
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The revised FFT uses a redundant sequence of twiddle factors to allow a
linear access through the data. This linear access enables data and
instruction level parallelism.
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The butterfly is bit reversed; i.e. the inner 2 points of the butterfly are
crossed over. This makes the data come out in bit reversed rather than in
radix 4 digit reversed order. This simplifies the last pass of the loop. The
BITR instruction does the bit reversal out of place.
Cycles ceil[log (nx) − 1] * (8 * nx/8 + 24) + 5.25 * nx/4 + 31
4
Codesize 640 bytes
(nx) − 1 stages of radix-4 transform and performs
4
C64x+ DSPLIB Reference
DSP_fft16x16r
4-23