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interrupt service table (IST) A table containing a corresponding entry for
each of the 16 physical interrupts. Each entry is a single-fetch packet and
has a label associated with it.
Internal peripherals: Devices connected to and controlled by a host device.
The C6x internal peripherals include the direct memory access (DMA)
controller, multichannel buffered serial ports (McBSPs), host port
interface (HPI), external memory-interface (EMIF), and runtime support
timers.
IST: See interrupt service table.
least significant bit (LSB): The lowest-order bit in a word.
linker: A software tool that combines object files to form an object module,
which can be loaded into memory and executed.
little endian: An addressing protocol in which bytes are numbered from right
to left within a word. More significant bytes in a word have
higher-numbered addresses. Endian ordering is specific to hardware
and is determined at reset. See also big endian.
maskable interrupt: A hardware interrupt that can be enabled or disabled
through software.
memory map: A graphical representation of a computer system's memory,
showing the locations of program space, data space, reserved space,
and other memory-resident elements.
memory-mapped register: An on-chip register mapped to an address in
memory. Some memory-mapped registers are mapped to data memory,
and some are mapped to input/output memory.
most significant bit (MSB): The highest order bit in a word.
m-law companding: See compress and expand (compand).
multichannel buffered serial port (McBSP): An on-chip full-duplex circuit
that provides direct serial communication through several channels to
external serial devices.
multiplexer: A device for selecting one of several available signals.
Glossary
Glossary
C-7
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