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3.1.1 PCI-X To VME Bridge (Tsi148) Software Guidelines
Programmers writing code or using GE Intelligent Platforms Board Support
Packages for the Tsi148 Bridge as used on the V7865 single board computer, must
be aware of requirements of the Tsi148 based PCI-X to VME architecture.
The V7865 PCI-X to VME Interface uses the Tundra Tsi148 2eSST Bridge. This
architecture interfaces the VME to the onboard SBC PCI-X bus. In doing so, the
user must be aware of the following guidelines as related to Software
programming of the Tsi148:
Shared V7865 Memory: Any V7865 DRAM memory made available to another
VME master through the Tsi148 is subject to dead lock that may cause a VME bus
error unless specific precautions are taken. If onboard DRAM memory is slaved to
the VME, and a program on the V7865 with slaved memory attempts to write
(from the processor) to the VME through the Tsi148, then the user must first
request ownership of the VME through the Device Wants Bus (DWB) Bit in the
Tsi148, and be granted the VME, prior to doing writes to the Tsi148. (Note, please
see the Tsi148 Manual and Errata regarding the requirements to use the DWB bit
of the Tsi148). The user may also implement other methods of gaining ownership
of the VME, such as Tsi148 semaphores. But, regardless of the method used, when
using shared memory, the user must gain exclusive VME ownership prior to
generating asynchronous VME writes.
Extremely Long VME Slave Response Time: VME slave devices (or VME BERR
conditions) that have a DTAK (or BERR) response time of greater than 16μs can
cause Bridge Ordering rule issues with intermixed reads and writes through the
Tsi148. If the SBC user wishes to do an extended number (larger than the depth of
the Tsi148 write post buffer) of consecutive writes from the processor to the VME
through the Tsi148, and those writes can be intermixed with reads from another
task, then the user must verify that all slaves within the system have DTACK
response time of less than 16μs, and that the VME BERR timer of the system is set
to 16μs max. Also it is suggested that prior to doing any large VME transfer, the
users should first request ownership of the VME through the DWB Bit in the
Tsi148, and be granted the VME, prior to doing writes to the Tsi148. (Note, please
see the Tsi148 Manual and Errata regarding the requirements to use the DWB bit
of the Tsi148). The user may also implement other methods of gaining ownership
of the VME, such as Tsi148 semaphores. But, regardless of the method used, when
generating an extended number of consecutive processor to VME writes (larger
than the depth of the Tsi148 write post buffer), the user must gain exclusive VME
ownership prior to generating these asynchronous VME writes.
42 V7865 Hardware Reference Manual
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NOTE
Failure to implement the procedures outlined above may cause some system implementations to
lockup or generate unwanted VME errors.
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