Ipmi And Hot Swap; Hot Swap Controller; Cpld; Pci 6254 Cpci Bus Bridge - GE C2K Hardware Reference Manual

4.16 IPMI and Hot Swap

The C2K includes cPCI full Hot Swap and IPMI features with the following components.
• Hot Swap Controller (HSC)

• CPLD

• PCI 6254 cPCI Bus Bridge (backplane bridge)
• C8051F127 Microcontroller (C8051)

4.16.1 Hot Swap Controller

The LTC4244-1 Hot Swap Controller (HSC) allows the C2K to be installed or removed from a
CompactPCI chassis while the chassis is powered-up. The HSC provides the PCI signal
pre-charge voltage and controls the C2K's main power. The HSC also monitors the main on-board
voltage rails: +5V, +3.3V, and ±12V.
4.16.2 CPLD
The C2K provides a small CPLD to assist the HSC. The CPLD monitors the M66EN, PCIXCAP,
BDSEL#, and PCI_RST# signals from the backplane to control the blue front-panel Hot Swap
LED and generates the HEALTHY# signal to the backplane. The CPLD also initiates the board
power-on sequencing.

4.16.3 PCI 6254 cPCI Bus Bridge

The PCI 6254 provides ENUM# support and monitors ejector handle status and Geographic
Address inputs. It also contributes to the software control of the blue front-panel Hot Swap LED.

4.16.4 C8051 Microcontroller

The IPMI Controller consists of the C8051F127 Microcontroller (C8051), support logic, and
GEIP's IPMI software. The C8051 Microcontroller includes the following features:
• 128kbytes of internal flash storage for program code
• 8kbytes of internal SRAM for scratchpad and general use
• Full-duplex asynchronous UART
• Five counter/timers
• 24.5MHz oscillator
• Watchdog timer
• JTAG/Debug interface
C8051 8-bit I/O Ports
The C8051 Microcontroller includes four 8-bit I/O ports. Port 0 and Port 1 provide I/O for
external SRAM and UART signals. Port 0 also provides the on-board SPI Bus and IIC Bus
interface used for IPMI features. Port 1 provides several device chip selects and a serial interface
for communicating to MPC7448 processor. Port 2 and Port 3 are configured as multiplex
address/data buses for the external SRAM. lists the pin assignments for the four I/O ports.
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