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3.3 Timers
3.3.1 General
The V7865 provides four user-programmable timers (two 16-bit and two 32-bit)
which are completely dedicated to user applications and are not required for any
standard system function. Each timer is clocked by independent generators with
selectable rates of 2 MHz, 1 MHz, 500 kHz and 250 kHz. Each timer may be
independently enabled and each is capable of generating a system interrupt on
timeout.
Events can be timed by either polling the timers or enabling the interrupt
capability of the timer. A status register allows for application software to
determine which timer is the cause of any interrupt.
3.3.2 Timer Control Status Register 1 (TCSR1)
The timers are controlled and monitored via the Timer Control Status Register 1
(TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits
in this register are as follows:
Table 3-2 Timer Control Register 1 (TCSR 1)
Field
Timer 1 Caused IRQ
Timer 1 Enable
Timer 1 IRQ Enable
Timer 1 Clock Select
Timer 2 Caused IRQ
Timer 2 Enable
Timer 2 IRQ Enable
Timer 2 Clock Select
Timer 3 Caused IRQ
Timer 3 Enable
Timer 3 IRQ Enable
Timer 3 Clock Select
Timer 4 Caused IRQ
Timer 4 Enable
Timer 4 IRQ Enable
Timer 4 Clock Select
Reserved
All of these bits default to "0" after system reset.
Each timer has an independently selectable clock source which is selected by the
bit pattern in the "Timer x Clock Select" field as follows:
Table 3-3 Timer x Clock Select Field
Clock Rate
2 MHz
1 MHz
500 kHz
250 kHz
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Bits
TCSR1[0]
TCSR1[1]
TCSR1[2]
TCSR1[4..3]
TCSR1[8]
TCSR1[9]
TCSR1[10]
TCSR1[12..11]
TCSR1[16]
TCSR1[17]
TCSR1[18]
TCSR1[20..19]
TCSR1[24]
TCSR1[25]
TCSR1[26]
TCSR1[28..27]
All Other Bits
MSb
LSb
0
0
0
1
1
0
1
1
Read or Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Embedded PC/RTOS Features 45
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