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3.3.7 Timer 1 & 2 Current Count Register (TMRCCR12)
The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count
Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The
mapping of bits in this register are as follows:
Table 3-8 Timer 1 & 2 Current Count Register (TMRCCR12)
Field
Timer 2 Count
Timer 1 Count
When either field is read, the current count value is latched and returned. There
are two modes that determine how the count is latched depending on the setting
of the "Read Latch Select" bit in the WDT Control Status Register (CSR2). See the
CSR2 register description for more information on these two modes.
3.3.8 Timer 3 Current Count Register (TMRCCR3)
The current count of Timer 3 may be read via the Timer 3 Current Count Register
(TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of
bits in this register are as follows:
Table 3-9 Timer 3 Current Count Register (TMRCCR3)
Field
Timer 3 Count
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of
the "Read Latch Select" bit in the WDT Control Status Register (CSR2). See the
CSR2 register description for more information on these two modes.
3.3.9 Timer 4 Current Count Register (TMRCCR4)
The current count of Timer 4 may be read via the Timer 4 Current Count Register
(TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of
bits in this register are as follows:
Table 3-10 Timer 4 Current Count Register (TMRCCR4)
Field
Timer 4 Count
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of
the "Read Latch Select" bit in the WDT Control Status Register (CSR2). See the
CSR2 register description for more information on these two modes.
3.3.10 Timer 1 IRQ Clear (T1IC)
The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by
Timer 1. Writing to this register, located at offset 0x30 from the address in BAR2,
causes the interrupt from Timer 1 to be cleared. This can also be done by writing a
"0" to the appropriate "Timer x Caused IRQ" field of the timer Control Status
Register (CSR1). This register is write only and the data written is irrelevant.
48 V7865 Hardware Reference Manual
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Bits
TMRCCR12[31..16]
TMRCCR12[15..0]
Bits
TMRCCR3[31..0]
Bits
TMRCCR4[31..0]
Read or Write
Read Only
Read Only
Read or Write
Read Only
Read or Write
Read Only
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