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12.3.7
EVM Resource Allocation
The UCD3138PSFBEVM-027 is controlled by a control card, the UCD3138CC64EVM-030, through two
40-pin connectors, P1 and P2.
board.
Header Pin No.
P1-1
P1-2
P1-3
P1-4
P1-5
P1-6
P1-7
P1-8
P1-9
P1-10
P1-11
P1-12
P1-13
P1-14
P1-15
P1-16
P1-17
P1-18
P1-19
P1-20
P1-21
P1-22
P1-23
P1-24
P1-25
P1-26
P1-27
P1-28
P1-29
P1-30
P1-31
P1-32
P1-33
P1-34
P1-35
P1-36
P1-37
P1-38
P1-39
P1-40
P2-01
P2-02
SLUUAK4 – August 2013
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Description of the Digital Phase-Shifted Full-Bridge Converter
Table 6
lists the definitions of P1 and P2 on the UCD3138PSFBEVM-027
Table 6. P1 and P2 Pin Assignment
UCD3138 Pin
Name
DPWM_0A
DPWM0A, slope generation
DPWM_0B
DPWM0B, controls the secondary-sync FET, QSYN1, 3.
DPWM_1A
DPWM1A, slope generation
DPWM_1B
DPWM1B, controls the secondary-sync FET, QSYN2, 4.
DPWM_2A
DPWM2A, controls the primary-side FET, QT2.
DPWM_2B
DPWM2B, controls the primary-side FET, QB2.
DPWM_3A
DPWM3A, controls the primary-side FET, QB1.
DPWM_3B
DPWM3B, controls the primary-side FET, QT1.
DGND
Digital ground (GND)
DGND
Digital ground (GND)
GPIO08
ON/OFF
GPIO09/FLT1B
GPIO_ORING_CTR
GPIO10
Failure
GPIO11/FLT2B
P_GOOD
GPIO28
Not used
GPIO29
Not used
GPIO30
Not used
GPIO31
Not used
GPIO32/FLT4A
I_FAULT
GPIO33/ FLT4B
LATCH_ENABLE
GPIO26
Not used
GPIO22
Not used
GPIO24
Not used
GPIO23
Not used
GPIO18/PWM1
AC_FAIL
GPIO19/PWM2
ACFAILIN
GPIO20
Not used
GPIO21
Not used
GPIO34
Not used
GPIO35
Not used
GPIO16/SCI_TX
SCI transmit
GPIO17/SCI_RX
SCI receive
GPIO25
Not used
GPIO27
Not used
GPIO27
Not used
RESET*
Not used
DGND
Digital ground (GND)
DGND
Digital ground (GND)
VauxS
External 12-V DC supply
Not connected to
Not used
UCD3040
AGND
Analog ground (GND)
ADCREFin
Not used
Copyright © 2013, Texas Instruments Incorporated
Usage Description
Using the UCD3138PSFBEVM-027
31
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