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When both QB1 and QT2 turn on, the input voltage Vbus is applied to the power transformer and energy
is transferred to the output. During this period, QSYN1 and QSYN3 are turned off and power is transferred
through L1 to the output. The return current flows through QSYN2 and QSYN4, which are turned on, and
then the current flows back to the secondary side of the main transformer. When QB2 and QT1 are both
on, the bus voltage is applied to the power transformer in the opposite direction. In this case, QSYN2 and
QSYN4 are turned off and power is transferred through L1 to the output. The return current flows through
QSYN1 and QSYN3, which are turned on, and then flows back to the main transformer. When all four
switches on the primary side are turned off, the secondary side works in a freewheeling mode, meaning all
sync FETs are turned on and the inductor current flows through the switches. See
references containing additional details about the phase-shift full-bridge converter.
Because the digital controller generating the six DPWMs in on the secondary side and four of the power
switches are on the primary side, the converter requires an isolation component to cross the boundary.
Pulse transformers, T3 and T4, transmit the gate signal and drive the primary-side power MOSFETs.
These transformers are used because they are simple and low cost although they typically require more
space than digital isolators. Two drives, U5 and U6, drive the gate-drive transformers from the secondary
side. The leakage inductance of the gate transformer oscillates with other capacitors in the gate-drive
circuit during dead time. If the leakage inductance oscillates with other capacitors, a glitch can occur. A
negative voltage is provided by the components D20 and C36 for QT1. Other switches use the same
circuit that generates negative current. The secondary-side switches do not require isolation. Two ICs, U3
and U8, directly drive these switches.
The dead time between all switches is important to achieve zero-voltage switching based on different
operation conditions such as load current and input voltage.
For peak-current-mode control, slope compensation is important to stabilize the loop and avoid the non-
periodic ripple of the output voltage. The slope is generated either internally or externally. If the slope
compensation is generated externally, DPWM0A and DPWM1A are used. In this case, install the jumpers
between Pin1 to Pin2 and between Pin5 and Pin6 for proper operation. Install Q1, Q2, Q4, and Q8 to
generate the slope.
External slope-compensation circuits require many external components. In default, internal slope
compensation is used. The controller generates the slope and adds the slope on the filter output of the
voltage loop. EAP2 requires a pullup resistor to provide over 100-mV DC offset voltage, which is important
to stabilize the loop at the small duty.
12.3.2
Bias Power Supply
The bias supply is a flyback converter using the UCC28600 controller from TI. The bias is an independent
daughter-card, the PWR050. The design files (SLUR924) are located in the UCD3138PSFBEVM-027
product folder on www.ti.com.
There is one 12-V output (PN3-PN4) on the primary side and one 12-V output (PN5-PN7) on the
secondary side. The feedback signal is taken from the secondary 12-V output. The controller requires +3.3
V, which is derived from the secondary 12-V output through a LDO regulator (U2).
SLUUAK4 – August 2013
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Description of the Digital Phase-Shifted Full-Bridge Converter
Figure 25
shows the schematic of the PWR050.
Copyright © 2013, Texas Instruments Incorporated
Section 15
for a list of
Using the UCD3138PSFBEVM-027
27
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