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Description of the Digital Phase-Shifted Full-Bridge Converter
12.3 EVM Hardware — Introduction
This section describes the EVM hardware functions.
12.3.1
Power Stage
This EVM implements topology for a phase-shifted full-bridge DC-DC converter. The key waveforms
generated by the UCD3138 to control the phased-shifted power stage are shown in
Section 4
for the complete schematics. On the primary side, QT1, QB1, QT2, and QB2 are the power
switches, L2 is a resonant inductor (often called shim inductor), and T1 is the main transformer. D9 and
D10 are clamping diodes. T2 is a current transformer for sensing primary-side current and is located on
the high side. T5 is not used and is shorted by jumper J10.
The secondary side is configured as a central-tap synchronous rectifier comprised of an output choke
(L1), output capacitor (C4 and C62), and synchronous MOSFETS (QSYN1, QSYN2, QSYN3 and
QSYN4). Q6 and Q10 are oring FETS for hot swap. T3 and T4 are gate transformers to drive primary-side
power MOSFETs and provide isolation boundary. Two gate drivers (U4 and U5) are used for driving the
gate transformers. Two low-side drivers, U3 and U8, are used for driving the secondary-side synchronous
MOSFETs.
DPWM3A
(QB1)
DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTran
s
DPWM1B
(QSYN1,3)
DPWM0B
(QSYN2,4)
IPRI
Figure 24. Driving Scheme of Phase-Shifted Full-Bridge Control
The following lists the DPWM configuration for the phase-shift full bridge converter:
DPWM3A to VGS_QB1
DPWM2A to VGS_QT2
DPWM1B to VGS_QSYN2 and QGS_QSYN4
26
Using the UCD3138PSFBEVM-027
DPWM3B to VGS_QT1
DPWM2B to VGS_QB2
DPWM0B to VGS_QSYN1 and QGS_QSYN3
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Figure
24. See
SLUUAK4 – August 2013
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