Chapter 2: Functional Description; Micro Channel Memory Cycles; Micro Channel I/O Cycles - 3Com EtherLink/MC Technical Reference Manual

EtherLink/MC:
2
Functional Description
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Chapter 2: Functional Description
This section describes, in detail, the purpose, features and functionality of the several functional
secdons of the EtherLink/MC adapter.
The EtherLink/MC adapter responds to three different types of Micro Channel cycles. These are:
memory, I/O and setup.
Micro Channel Memory Cycles
EtherLink/MC adapter decodes one of four possible 24K memory address ranges. The base address
of these memory ranges are: C0000, C8000, D0000 or D8000. The first 16K of the memory range is
dedicated to to accessing the 16K window of the adapter's packet buffer RAM. Which of the four
16K banks is accessible through the window is controlled with the +BS0 and +BS1 bank select bits
in the Control Register (I/O base + 6). For normal operation of the 16K adapter, +BS0 and +BS1
should both be set to 1 (bank 3). Either 16-bit or 8-bit cycles may be used to access the packet
buffer memory.
The last 8K of the memory range is used to access the EtherStart BIOS ROM for booting up the host
system using a boot volume from a network resource. The last 8K of the memory range is consumed
by the adapter for this purpose regardless of whether or not a ROM is installed in the adapter's
EtherStart ROM socket. Though the ROM is only 8 bits wide, the Micro Channel supports 16-bit
and 32-bit accesses to the ROM by automatically packing the appropriate number of bytes together
to form the desired word. This process is transparent to the host processor.
Micro Channel !/0 Cycles
EtherLink/MC adapter provides four different possible I/O base addresses (0300, 1300, 2300 and
3300). Eight byte-wide I/O registers are designed into the adapter. The first six contain the
adapter's unique II:~EE network address number (48 bits total)~ The next register (I/O base + 6) is
the control and status register. The last register contains a version number port. The least significant
4 bits of this register contain the current version number. Adapters that contain changes that might
affect software will have different version numbers.
All of the I/O registers on the adapter arc 8-bit registers. 16-bit I/O cycles to these registers is
supported and will result in pairs of registers being selected in sequence.