3Com EtherLink/MC Technical Reference Manual page 12

A
EtherLinldMC:
Register Definitions
A-2
Register 6: EtherLink/MC Adapter Control & Status
7 6 5 4 3 2
1 0
I
+CA
+LBK * +INT +INTE +BS1 +BS0 I
I I I
I
Control and Status ~Register Bits
+BS+BS(1,0) RAM Bank Select. (Read/Write) These bits are used to select which 16K bank of the
Packet Buffer will be available through the 16K access window. Adapters with 16K
packet buffers must select bank 3 for normal operation.
NOTE: the power-up condition of these bits is for bank 0 to be selected. This means
that until bank 3 is selected the host system cannot access the RAM on 16K adapters.
00 = bank 0
01 = bank 1
10 = bank 2
11 = bank 3 (Required setting for 16K adapters)
Interrupt Enable. (Read/Write) This bit is set when it is desired to have the 82586's
interrupt line generate a Micro Channel interrupt. For normal operation it is not
necessary to ever clear the +INTE bit. Proper use of the 82586 will prevent the
generation of interrupts. The +INTE bit should generally be set and only cleared for
diagnostic or development applications.
+INT
Interrupt Active. (Read Only) This status bit is set when the 82586 asserts its
interrupt line. This status bit is not latched and reflects the immediate condition of
the 82586's interrupt line. Use of this bit is intended primarily for diagnostic and/or
development applications.
+LBK
Loop Back Enable. (Read/Write) Setting the Loop Back bit causes the Manchester
Eneoder/Decoder to enter the loopback mode. This bit must be cleared to a zero for
normal network operation.
+CA Channel Attention. (Read/Write) Writing a one to this bit asserts the channel
attention signal to the 82586. This bit must be reset to a zero no less than 500
nanoseconds after it was set. Because the 82586 responds to the falling edge of
Channel Attention, it is recommended that it be deasserted as soon as possible after
the minimum time has elapsed in order to minimize 82586 response time.