Multiple Block Batch Read And Batch Write - Mitsubishi MELSEC Q Series Reference Manual

3.3.2 Multiple block batch read and batch write

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3 WHEN COMMUNICATING USING THE QnA COMPATIBLE 3E/3C/4C FRAMES OR 4E FRAME
The examples shown in this section explain the control procedure for reading and
writing by randomly designating multiple blocks, where one block consists of n points
of a bit device memory (1 point = 16 bits) and a word device memory (1 point = 1 word).
This function is used when accessing the Q/L/QnACPU.
The following modules are accessible:
• The Q/LCPU on the station where the C24/E71 is loaded (local station), and
the Q/LCPU on the station connected on a Q/L series supporting network
system (CC-Link IE Controller Network, CC-Link IE Field Network,
MELSECNET/H, MELSECNET/10, or Ethernet) (other station)
• The QnACPU (listed below) (other station), and the QCPU/QnACPU (listed
below) on the station connected on a QnA series supporting network system
(MELSECNET/10, or Ethernet) (other station)
Function
Multiple block batch read/write
This function is added to the products that have 9707 B or later on the package marking and DATE
column of the rated plate.
(9707: Date of manufacture, B:Functional version (marked for version B or later))
POINT
When reading or writing contacts or coils for T, ST, or C, use the number of bit
device blocks.
Programmable controller CPU
QnA Q2AS (H)
(Products 9707B or later)
Q4AR
(All accessible)
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