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hilscher netX 90 Design-In Manual

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Design-In Guide
netX 90
Hilscher Gesellschaft für Systemautomation mbH
www.hilscher.com
DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public

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Summary of Contents for hilscher netX 90

  • Page 1 Design-In Guide netX 90 Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...

  • Page 2: Table Of Contents

    List of revisions..........................5 References to documents ......................5 Basic concepts ............................6 netX 90 – introduction ........................6 netX 90 – use cases ........................7 Design checklist ..........................8 Basic circuits ............................10 Power supply ..........................10 3.1.1 Integrated core voltage regulator ..................... 10 Brown-Out Detector (BOD) ......................
  • Page 3 6.2.4 Clock circuits ........................... 55 6.2.5 Ethernet interface ..........................56 6.2.6 Memory bus ............................. 58 6.2.7 Planes ............................. 58 6.2.8 VIAs and signal fan out under netX 90 .................... 59 Appendix ............................... 60 List of tables ..........................60 List of figures ..........................61 Legal notes ...........................

  • Page 4: Introduction

    Hilscher devices (e.g. Gateways). We therefore recommend you to check with Hilscher Sales if there is already a solution for your problem. Moreover, Hilscher offers several custom design services for netX hardware and software, as well as manufacturing services, providing an easy way to your custom product.

  • Page 5: List Of Revisions

    This document refers to the following documents: Hilscher Gesellschaft für Systemautomation mbH: Technical Data Reference Guide, netX 90, Revision 2, English, 2018. Hilscher Gesellschaft für Systemautomation mbH: Getting started, netX Studio CDT, netX 90 development, Revision 4, English, 2018. Table 2: References to documents...

  • Page 6: Basic Concepts

    2 Basic concepts netX 90 – introduction The netX 90 is housed in a 144-pin BGA package and includes two Arm Cortex-M4 cores, on-chip Flash memory, Fast Ethernet PHYs, and a DC/DC converter with POR circuit to reduce the BOM costs for the hardware interface to a few passive components.

  • Page 7: Netx 90 - Use Cases

     a companion chip with host interface Hilscher provides the range of software protocol stacks for communication tasks as a prebuilt firmware that is generally the same for both use cases apart from the user configuration. A communication firmware consists of three parts: 1.

  • Page 8: Design Checklist

    8/66 Design checklist Hilscher supplies the software stacks for all widely used communication protocols, including OPC UA and MQTT for IIoT connectivity, as a loadable firmware (LFW) as explained in section Firmware overview and resources on page 51. LFW variants differ in terms of functionality, protocols, and memory resources.
  • Page 9 Unused components: Check details for ADC, BOD, and Ethernet PHY if unused Finish Figure 2: Checklist for a netX 90 design netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 10: Basic Circuits

    74438323100. The capacitor is a ceramic type (X5R/X7R). The selected 10 µH inductor and 10 µF output capacitor ensure that the integrated DC/DC delivers supported output currents for the core voltage of the netX 90 only Should other parts of the embedded system require 1.2 V, we recommend you to implement a separate voltage supply.

  • Page 11: Brown-Out Detector (Bod)

    If the BOD function is not used, connect it to +3.3V. Do not leave this pin unconnected! DDIO netX 90 BS-NX90BOD-UNUSED-V1 Figure 5: netX 90 Brown-Out Detector not used netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 12: Power-On Reset And Reset In

    Basic circuits 12/66 Power-on reset and reset in The netX 90 has an integrated Power-On Reset (POR) circuit and optionally provides a Reset Input (RST_INn) pin. Parameter Conditions Unit Supply voltage V DDIO POR level Ramp from 0 to 3.3 V 2.73...

  • Page 13: System Clock

    13/66 System clock The netX 90 uses an internal oscillator with an external crystal to generate the 25 MHz base clock. A PLL generating all chip-internal clocks will stabilize this clock. Figure 6 shows the circuit of the system clock generation:...

  • Page 14: Boot Sequence

    For details about the ROM code boot sequence, see reference [1]. 3.5.1 Configuration pins The SYS LED at RDY and RUN indicate the operating status of the netX 90. To enter the console mode or the alternative boot mode, the ROM code uses the following ways: ...

  • Page 15: Console Mode

    Is the console mode interface for the UART mandatory in embedded designs? The netX 90 chip can be programmed via JTAG/SWD as long as the debug interface is not locked down by chip level security settings. If the debug interface is locked by the user configuration, the user can optionally unlock the device again via a secure UART connection using his private key.

  • Page 16: System Rdy/Run Led

    ROM code active Table 5: RDY / RUN LED colors Designers can use LEDs with other colors, but we recommend using the Hilscher definition. Especially when interpreting blink codes for troubleshooting, it is helpful if customer and Support see the same colors.

  • Page 17: External Memory

    Hilscher’s component verification flow. The list of components: https://kb.hilscher.com/display/NETX/Supported+hardware+components The list of recommended components for the netX 90 will be updated at a later date. Until further notice, follow the recommendations of this document or contact our netX Support.

  • Page 18: Serial Memory Interface

    3.6.1 Serial memory interface The netX 90 has a dedicated SPI/QSPI controller which supports execute in place (XiP), is not shared with any other peripheral pin functions, and thus to be used for external serial flashes. Depending on the use case, the SPI/SQI controller can serve the communication or application side of the chip.

  • Page 19: Parallel Memory Interface

    3.6.2 Parallel memory interface The netX 90 contains two external parallel memory interface controllers that are mapped to the same signal pins. The extension bus connects to external parallel Flash or SRAM. The SDRAM controller connects to either 8-bit or 16-bit SDRAM.
  • Page 20 90 netX 90 BS-NX90SDRAM-V1 Figure 9: netX 90 SDRAM 1x 16-bit, 1x 8-bit Q1: In the meantime DDR-3 RAM or higher is state of the art. Why are the netX chips equipped with an outdated SDRAM interface only? Well, SDRAM isn’t really outdated. DDR RAM technology was invented for the short-...

  • Page 21: Host Interface

    21/66 Host interface The netX 90 can be used as a companion chip with host interface and paired with any application host, i.e. FPGA, MCU, MPU, ASIC, DSC, etc. The following host interface options are supported: Two serial DPM (SPM) interfaces: ...

  • Page 22: Dual-Port Memory

    3.7.1.1 8/16-bit data width and dual-port memory size In DPM mode, the netX 90 supports 8 or 16-bit data widths. In general, the minimum addressable DPM range is 2 KB and the integrated DPM size is 32 KB. A standard Hilscher firmware with one communication channel uses a 16 KB DPM software layout by default.

  • Page 23: Non-Multiplexed Mode

    DPM_CS DPM_BHE DPM_RD DPM_WRL DPM_WRH RDY/BUSYn DPM_RDY DPM_DIRQ D0-15 DPM_D0-15 Host netX 90 BS-NX90DPM_Intel_NonMux16-V1 Figure 11: Intel interface, 16-bit, non-multiplexed netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...
  • Page 24 DPM_CS DPM_BHE RD/WRn DPM_RD DPM_RDY DPM_DIRQ D0-7 DPM_D8-15 D8-15 DPM_D0-7 Host netX 90 BS-NX90DPM_MotorolaCF_NonMux_16-V1 Figure 13: Motorola ColdFire, 16-bit, non-multiplexed netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...
  • Page 25 RD/WRn DPM_RD DTACK DPM_RDY IPL0 DPM_DIRQ D0-7 DPM_D8-15 D8-15 DPM_D0-7 Host netX 90 BS-NX90DPM_MotorolaM_NonMux16-V1 Figure 14: Motorola M68000, 16-bit, non-multiplexed netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 26: Multiplexed Mode

    DPM_ALE DPM_RD DPM_WRL DPM_WRH RDY/BUSYn DPM_RDY DPM_DIRQ AD0-15 DPM_D0-15 Host netX 90 BS-NX90DPM_Intel_Mux16-V1 Figure 16: Intel interface, 16 bit, multiplexed netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 27: Ready/Busy Signal

    Our standard firmware uses the Busy mode with an active low signal. All schematics of this manual show the Ready/Busy signal as DPM_BUSYn. The timing diagrams of the netX 90 Technical Data Reference Guide often show this signal as RDY (Ready mode / active high).

  • Page 28: Serial Port Memory (Spi/Qspi Access To Dpm)

    3.7.2 Serial port memory (SPI/QSPI access to DPM) The netX 90 supports the connection between application host and netX DPM via SPI or QSPI where the netX is the slave. Table 11 lists the signals for SPM0 (serial DPM0 interface):...

  • Page 29: Pio Signals

    Every pin of the host interface (HIF) can be used as a general HIF_PIO pin but without IRQ support. However, the netX 90 provides up to 29 additional PIO pins with IRQ functionality (edge or level-triggered) available as pin sharing option defined in the BGA pinout.

  • Page 30: Multiplexed Io Matrix (Mmio)

    30/66 Multiplexed IO matrix (MMIO) netX 90 provides a range of on-chip peripherals for application developments. A subset of these peripherals is available as pin sharing option defined in the BGA pinout and/or can be mapped to any of the 18 MMIO pins. Table 12 list all MMIO peripherals.
  • Page 31 HIF pio input sampling enable xc_sample0 Trigger/latch unit xc_sample1 Trigger/latch unit xc_trigger0 Trigger/latch unit xc_trigger1 Trigger/latch unit Table 12: Multiplex matrix signals netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 32: General Purpose Ios

    GPIO IRQ IRQs and IMSKs GPIO_IRQ_RAW & from other GPIOs Set/reset by GPIO_IRQ_MASK_SET/RST GPIO_IRQ_MASK GPIO_IRQ_MASKED BD-NX51&52GPIO-V1 Figure 19: GPIO block diagram netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 33: Serial Interfaces

    3.11.1 UARTs In total, the netX 90 provides three UARTs (each with RX, TX, RTSn, CTSn) interfacing directly to common RS-232 or RS-485 transceivers (see Figure 20). The peripheral named UART must be used if the console mode via UART is required. The Hilscher loadable firmware (LFW) may also use the same UART as a diagnostic interface.

  • Page 34: Spi

    Basic circuits 34/66 3.11.2 The netX 90 features four SPI units. SPI0_APP and SPI2_APP are both available as predefined pin sharing options. SPI1_APP and SPI_xPIC_APP can both be mapped to any of the 18 MMIO pins. Basic technical data for SPI master and slave functionality ...

  • Page 35: I2C

    35/66 3.11.4 The netX 90 provides two I2C units for application developments. I2C_APP is available as a predefined pin sharing option or can be mapped to any of the 18 MMIO pins. I2C_xPIC_APP can be mapped to any of the 18 MMIO pins.

  • Page 36: Io-Link

    Basic circuits 36/66 3.12 IO-Link The netX 90 has an IO-Link controller that supports IO-Link version V1.1 with 8 channels. +3V3 netX 90 +24V L6360 MICROELETRONICS Connector Interrupt L+ on/off generation EN_L+ IO-LINK controller 8 KB (FSM) TX_OE Status/Config Data TCM...

  • Page 37: Analog To Digital Converter

    Basic circuits 37/66 3.14 Analog to digital converter The netX 90 has four independently operating 12-bit single-ended SAR ADC units. The reference voltage for the analog-to-digital conversion is supplied by V and V (see Figure 22). The REF_ADC SS_REF selection of the reference voltage is programmable and can be provided internally from a 2.6 V reference buffer.

  • Page 38: Fieldbus Interfaces

    I/O signals (XMi_IO0 and XMi_IO1). Current fieldbus interfaces use only one of them. On the netX 90, the number of I/O signals has already been increased to a total of 5 signals for future use. Each xC unit also provides a clock input/output signal (XMi_ECLK) which allows synchronizing external hardware to the xC clock or feeding an external clock to the xC unit.

  • Page 39: Cc-Link Interface

    For Details refer to the DeviceNet specification 15n/1kV from the ODVA BS-NX90DeviceNet-V1 Figure 26: Basic circuit for netX DeviceNet interface netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 40: Profibus Interface

    Table 14: Status LEDs for fieldbus ports +3.3V netX 90 MLED0 COM0 +3.3V MLED1 COM1 BS-NX90COMLED-V1 Figure 28: Fieldbus status LEDs netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 41: Real-Time Ethernet (Rte) Interface

    41/66 3.17 Real-time Ethernet (RTE) interface The netX 90 has two integrated physical layer units (PHYs) for Ethernet communication that allows you to build systems with two Ethernet ports using only a few external passive components and transformer(s). You can operate the PHYs in the mode: Twisted pair (10BASE-T / 100BASE-TX) 3.17.1...
  • Page 42 J8064D628ANL ERNI: 203313 Q1: Why does the Ethernet PHY interface circuit of the netX 90 not use termination resistors connected in parallel? The integrated dual Ethernet PHY uses a voltage mode driver and not a current mode driver. The voltage mode driver uses integrated series termination resistors calibrated to 50 Ω...
  • Page 43 90 BS-NX90EthernetSinglePort-V2 Figure 30: netX 90 single-channel Ethernet circuit (Twisted pair) Q1: We do not stock 6.49 kΩ resistors. Can’t we use 6.2 kΩ/6.8 kΩ instead? The specified resistor values are taken directly from the specs of the internal PHY.

  • Page 44: Unused Ethernet Phys

    External Ethernet PHYs can be connected to the pins at MII0 and MII1. However, not all Ethernet PHYs available on the market are suitable for real-time Ethernet. According to preliminary evaluations, the TLK105 from TI seems a suitable candidate for the netX 90. netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public ©...

  • Page 45: Ethernet Status Leds

    MLED2 LINK0: green Ethernet Port 1, CH1 ACT1: yellow MLED3 LINK1: green Table 16: Status LEDs for Ethernet ports Mandatory design recommendations for the Hilscher loadable firmware Firmware overview and resources on page 51. +3.3V netX 90 ACT0 MLED2 LINK0 +3.3V...

  • Page 46: Real-Time Ethernet Protocol Status Leds

    MLED1 COM1 BS-NX90COMLED-V1 Figure 33: netX 90 RTE status LED schematic For COM0 and COM1 indicators/light pipes, use two red/green duo LEDs or two pairs of single LEDs. Place the LEDs of each pair close to each other. netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public ©...

  • Page 47: Real-Time Ethernet Synchronization Signals

    For RTE synchronization purposes, the netX 90 provides four additional signals, two input and two output signals. All four signals can be mapped to any of the 18 MMIO pins. The configuration can be carried out by using the hardware configuration tool integrated in the netX Studio CDT, see reference [2].

  • Page 48: Debug And Test Interfaces

    48/66 4 Debug and test interfaces The netX 90 implements a CoreSight debug and trace infrastructure. Either JTAG or Serial Wire Debug (SWD) and Trace Port Interface Unit (TPIU) can be used for firmware development as well as programming. In addition, the chip provides a boundary scan TAP in the JTAG chain.

  • Page 49: Jtag And Tpiu Interface (20-Pin)

    MLED1 / TRACE_DATA1 TRACEDATA[2] MLED2 / TRACE_DATA2 TRACEDATA[3] MLED3 / TRACE_DATA3 Table 20: 20-pin JTAG or SWD and TPIU connector pin assignment netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 50: Jtag Interface (10-Pin)

    50 MHz and multiplexed with JT_TDI. Due to the limited number of netX 90 pins, the trace signals are shared with functional MLED pins. The MLED[0...3] signals are mandatory for RTE link/activity LEDs and communication status LEDs. If trace support is required, the debugger must switch to SWD mode and enable the pin multiplex option for the trace signals.

  • Page 51: Firmware Overview And Resources

    51/66 5 Firmware overview and resources Firmware variants and use cases Preliminary information is available in the Hilscher knowledgebase. If you cannot access this information, contact the netX Support. Firmware programming and update Preliminary information is available in the Hilscher knowledgebase. If you cannot access this information, contact the netX Support.

  • Page 52: General Design Considerations

    General design considerations 52/66 6 General design considerations Preliminary information is available in the Hilscher knowledgebase. If you cannot access this information, contact the netX Support. Thermal behavior 6.1.1 Basics 6.1.2 Estimates 6.1.3 Recommendations 6.1.4 Rules of thumb netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public ©...

  • Page 53: Emc Behavior

    The following figure shows an approved 6-layer stack for netX designs: Figure 35: Approved netX PCB layer stack netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 54: Decoupling Capacitors

    90, connect the netX power and ground pins to the power and ground planes, connect the caps separately and always keep the traces as short as possible.

  • Page 55: Reset Lines

    The following picture shows a recommendation for placing and routing the oscillator components: Figure 37: Oscillator circuit with ground shield netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 56: Ethernet Interface

    The following figures show two examples of setups that keep the differential impedance of the signal pair around 100 Ohm: a) Edge-coupled surface micro strip Figure 38: Edge-coupled surface micro strip netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...
  • Page 57 2 resistors, the sum tolerance of both must be less than 1%!  Place the 10 nF capacitor in front of the transformer, not below it. netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 58: Memory Bus

    If you cannot avoid splitting planes, keep the traces well within the plane area. Do not route them at the edge or even outside the plane, as shown below: Figure 41: Routing Example netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 59: Vias And Signal Fan Out Under Netx 90

    SDRAM signal balls reside on the inner ball rings of the package. Standard “dog bone style” routing as shown below can be used to fan out the netX signals. Figure 42: VIA position and signal fan out under netX 90 Dimension...

  • Page 60: Appendix

    Table 11: SPI/QSPI to DPM (serial DPM) pin assignment ....................28 Table 12: Multiplex matrix signals ............................. 31 Table 13: Pin assignment analog input channels netX 90 ADCs ..................37 Table 14: Status LEDs for fieldbus ports ........................... 40 Table 15: Ethernet circuit component specification ......................42 Table 16: Status LEDs for Ethernet ports ..........................

  • Page 61: List Of Figures

    Figure 40: netX Memory Bus ............................. 58 Figure 41: Routing Example .............................. 58 Figure 42: VIA position and signal fan out under netX 90 ....................59 netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...

  • Page 62: Legal Notes

    The manual delivered with the product shall apply. Under no circumstances shall Hilscher Gesellschaft für Systemautomation mbH be liable for direct, indirect, ancillary or subsequent damage, or for any loss of income, which may arise after use of the information contained herein.
  • Page 63 Warranty Hilscher Gesellschaft für Systemautomation mbH hereby guarantees that the software shall run without errors in accordance with the requirements listed in the specifications and that there were no defects on the date of acceptance. The warranty period shall be 12 months commencing as of the date of acceptance or purchase (with express declaration or implied, by customer's conclusive behavior, e.g.
  • Page 64 Although the hardware and software was developed and tested in-depth with greatest care, Hilscher Gesellschaft für Systemautomation mbH shall not assume any guarantee for the suitability thereof for any purpose that was not confirmed in writing. No guarantee can be granted whereby the hardware and software satisfies your requirements, or the use of the hardware and/or software is uninterruptable or the hardware and/or software is fault-free.

  • Page 65: Registered Trademarks

    I2C is a registered trademark of NXP Semiconductors, formerly Philips Semiconductors. All other mentioned trademarks are property of their respective legal owners. netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

  • Page 66: Contacts

    Phone: +1 630-505-5301 E-Mail: info@hilscher.it E-Mail: info@hilscher.us Support Support Phone: +39 02 25007068 Phone: +1 630-505-5301 E-Mail: it.support@hilscher.com E-Mail: us.support@hilscher.com netX 90 | Design-In Guide DOC180501DG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2018...

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