Page 1 Technical data reference guide netX 90 Mass production Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 2: Table Of Contents
5.2.9 Serial dual-port memory timing ...................... 118 SQI/SPI ............................127 5.3.1 Overview ............................127 5.3.2 SQI ..............................129 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 3: Introduction
5.16 Quadrature decoder ........................190 5.17 Ethernet interface ........................191 5.18 Fieldbus interface ........................193 Debugging ............................194 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 4 Pin table sorted by pin number ....................204 Pin overview netX 90 ......................... 210 PAD type explanation ......................... 212 Schematic view of netX 90 PAD types ..................213 netX 90 package ........................214 Thermal resistance ........................216 Moisture sensitivity level ......................216 Appendix .............................
Page 5: Introduction
2018. Hilscher Gesellschaft für Systemautomation mbH: Design-In Guide, netX 90, Revision 2, English, 2018. Hilscher Gesellschaft für Systemautomation mbH: Getting started, netX Studio CDT, netX 90 development, Revision 4, English, 2018. Hilscher Gesellschaft für Systemautomation mbH: Programming Reference Guide, xPIC Instruction Set, netX 6/10/51/52, Revision 1, English, 2015.
Page 6: General Description And Features
As a result, the netX 90 provides a superior solution with an unmatched protocol flexibility for a variety of industrial slave or device applications in the process and factory automation.
Page 7: Doc160609Trg02En | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher
Suitable for any type of slave or device applications that require Industrial Ethernet or Fieldbus connectivity such as instrumentations, pneumatics, gateways, and many more. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 8: Block Diagram
16x App-LEDs -> (25MHz) VDDcore MEM16 IO-cfg (MUX, physical) VDDcore 18 MMIO Figure 1: Block diagram netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 9: Technical Data Netx 90
Mask ROM code, EMSA-PSS Built-in support Security levels, AHB Firewall Debug Debug / Trace JTAG/SWD, 4-bit TPIU Boundary scan JTAG netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 10 TBD (≤ 1 W) Package dimension 144-pin BGA, 10x10 mm , 0.8 mm Ball Pitch Table 3: Technical data netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 11: Netx 90 Signal Description
General description and features 11/227 netX 90 signal description This list groups the signals of the pin assignment table with the multiplexed signals (“shared with” operating modes), see chapter netX 90 package and signal information on page 198. General RST_IN_N Reset input...
Page 12 Serial Wire Debug data input output TRACE_DATA0…3 Trace port data TRACECLK Trace port clock TRACECTL Trace port control netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 13 Serial DPM (SQI), serial input/output data 0 DPM0+1_SPI_SIRQ Serial DPM (SPI, SQI), synchron interrupt request DPM0+1_SQI_SIO2+3 Serial DPM (SQI), serial input/output data 2+3 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 14 Encoder Data clock output ENDAT0+1_IN Encoder Data data input ENDAT0+1_OE Encoder Data output enable ENDAT0+1_OUT Encoder Data data output netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 15 CAN, application, receive data CAN0+1_APP_TX CAN, application, transmit data XC_TRIGGER0…1 RTE synchronization signals Table 4: netX 90 signal description netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 16: Core
3.1.2 xPIC CPU The xPIC (fleXible Peripheral Interface Controller) is a 32-bit RISC CPU from Hilscher optimized for fast and deterministic data processing. For instruction set, see reference [4]. The xPIC is used as peripheral controller for interfaces such as IO-Link, Ethernet MAC, etc. for which Hilscher provides low-level software drivers as HAL (Hardware Abstraction Layer) for the Cortex®-M4.
Page 17: Dmac
 Transfer direction The netX 90 includes two completely independent DMA controllers: One on the com-side and one on the app-side. Therefore, both DMACs are connected to different peripherals. Some peripherals are connected to both DMACs because they can be operated from either side (not at the same time, of course).
Page 18: Features
 Optimized memory copy function  Optimized peripheral data block transfer function  Periodical data transfer to slave/master netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 19: Functional Description
The source and destination address can be a memory region or a DMA-capable peripheral device of the netX. A system master programs the DMA controller via the AHBL slave interface. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 20: Data Transfer
If feasible, use separate memory areas for data storage and linked list information.  All memory and peripheral transactions should be 32-bit wide to improve bus efficiency. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 21: Dma Channel Priority
Crypto core The netX 90 has an integrated crypto core for SSL/TLS acceleration with up to RSA-4096, ECC- 512, AES-256, and SHA-512. The crypto core is used to support secure boot and secure update.
Page 22: Memory Map
0xff400000 eth_system 0xff480000 intlogic_app 0xff800000 xpic_app_config 0xff880000 xpic_app_system 0xff900000 debug_slave 0xffff8000 Table 6: Memory map of application side netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 23: Brown-Out Detector (Bod)
Depending on the division factor and the max. value of the monitored voltage, additional clamping may be required. The example above uses an external diode to V for this purpose. DDIO netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 24: Power-On Reset And Dc/Dc
Core 24/227 Power-on reset and DC/DC The netX 90 features an integrated DC/DC converter that generates the core voltage of the device and an integrated power watch that ensures the soft ramp-up/down with power-on-reset (POR) generation. The DC/DC step-down converter or buck converter uses an external coil for the current mode regulation which is automatically turned on after power-up.
Page 25: System Clock (Oscillator)
25/227 System clock (oscillator) The system oscillator circuit along with the internal PLL generates all internal clocks of the netX 90. For clock generation, either a quartz crystal with the internal oscillator circuit may be used or a quartz oscillator connected to the clock input pin.
Page 26: Interrupt Vectors
90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 27 78 … 95 software software Table 7: Interrupt vectors netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 28: Timer
TIMERi IRQ TIMERi OUT TIMERi_TH Threshold Register is also used as Capture Register Figure 7: Timer function diagram netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 29: Ieee 1588 System Time
CNT2 CNT T CNT1 Time fast slow Figure 9: Ongoing correction of time failure netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 30: Watchdog
If the watchdog is not enabled, this signal will remain low. Figure 11: Timing diagram of WDG_ACT netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 31: Internal Memory
3.12.1 Internal Flash The netX 90 features three identical 512 KB flash memory blocks with a user storage for program code and data (1024 KB Com and 512 KB App) of up to 1.5 MB in total. Each Flash memory block incorporates: ...
Page 32: External Memory
Overview Serial Flash can be connected to netX 90:   QSPI (XiP) Parallel external memory can be connected to the netX 90. The types to be connected are:  SDRAM,  SRAM or NOR Flash. The external memory controller supports 8 and 16-bit SRAM devices and 8 or 16-bit SDRAM devices.
Page 33: Features
Asynchronous Page mode (APM) supported  Optional ready/wait signal for external wait state generation providing signal filtering and timeout logic netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 34: Sdram Interface
(same addressing in split and non-split mode). netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 35 SD_WEN Only during SDRAM access, usable as FLASH/SRAM nWR simultaneously. Table 13: netX 90 SDRAM (Synchronous Dynamic Random Access Memory interface) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 36 Core 36/227 3.13.3.4 SDRAM component connection The following schematics show how to connect the SDRAM to netX 90 for 16 bit. SD_CSN Chip Select SD_A[12:0] Row/Column Address SD_BA[1:0] Bank Address SD_RASN SDRAM RAS SD_CASN SDRAM CAS SD_WEN SDRAM Write SD_DQM0...
Page 37 To benefit from the high-performance netX-external memory interface SDRAM controller, software memory mapping of all system masters running applications in SDRAM must be realized very accurately considering SDRAM properties. For netX 90, this basically means:  different masters should not work on SDRAM simultaneously ...
Page 38 No multi-master SDRAM usage 3.13.3.6 SDRAM data caches issues There is a 4 Dword read cache and a 4 Dword write cache implemented in netX 90 SDRAM memory interface to avoid burst runaways. Note: Caches are always enabled and cannot be disabled in the netX 90 memory interface.
Page 39 3.13.3.6.1 SDRAM timing parameters The following list provides an overview of timing parameters which can be programmed in netX 90 SDRAM controller configuration registers. Programming values depend on the SDRAM device used and must be taken from SDRAM device data sheet.
Page 40 Core 40/227 3.13.3.7 SDRAM timing This section provides netX 90 SDRAM-related timing characteristics. Note: In the following diagrams SDRAM signals RAS, CAS, WE are combined as “Command”. Initialization Figure 15 shows the SDRAM power-up initialization performed by the netX SDRAM controller.
Page 41 SD_DQM0..1 SD_A0..9, Bank SD_A11..15 A10S A10H A10S A10H all/ SD_A10 single SD_D0..31 Figure 16: SDRAM auto refresh generation netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 42 SD_A10 single SD_D0..15 Dout(n) Dout(n+1) Dout(n+2) Dout(n+3) RCDW Figure 18: SDRAM write timing (SD_CKE is always high) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 43 SD_D0..15 Din(n) Din(n+1) Din(n+2) Din(n+3) RCDR CAS Latency Figure 19: SDRAM read timing (SD_CKE is always high) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 44 SDRAM memory access. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 45 IO timing parameters for SDRAM All timings are related to the following SDRAM clock phase settings (to be set by programming register sdram_timing_ctrl of area hif_sdram_ctrl): hif_sdram_ctrl_sdram_general_ctrl.mem_sdclk_phase: hif_sdram_ctrl_sdram_general_ctrl.data_sample_phase: 0 Electrical characteristics of netX 90 SDRAM part (C 30 pF): Symbol Parameter Unit SDRAM clock (SD_CLK) cycle time 10.0...
Page 46: Sram/Flash Interface To Memory Interface Controller
APM is only available for chip select 0, not for the other chip-selects. The external memory interface controller and host interface memory controller both support this. All access timing can be configured in steps of netX 90 clock cycle i.e. 10 ns if not stepped down. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public ©...
Page 47 0..3 Figure 21: Sequential read pre and post pause not disabled (compatible with netX 50, 100, 500, default) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 48  a single master which, when running burst, exceeds the chip-select address area borders. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 49 A Figure 26: Pre and post-pause at chip-select or data direction change if 0 is not configured netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 50 0 (no_p_pre_seq_rd, no_p_post_seq_rd configuration bits). For APM-related performance issues, see section SRAM burst related performance issues on page 52. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 51 3.13.4.1.3 Ready signal – external wait state generation To allow an external device dynamic wait state generation, netX 90 provides a ready signal input. Ready signal usage can be configured for each chip-select individually. Ready activity level and signal filtering must be configured collectively for all chip-selects.
Page 52 (see reference [1]). For consecutive reads, addresses can be used in any order, i.e. addresses need not be incrementing. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 53 Core 53/227 3.13.4.3 SRAM / Flash timing This section provides netX 90 SRAM (e.g. NVRAM, Flash) related timing characteristics. CSSr CSHr next read or Chip-Select write access Read-Enable Ready/Busy busy busy ready busy busy ready RBsp RBsp Address Address Address...
Page 54 APM bursts are only supported for chip-select 0. 3.13.4.4 IO timing parameters for SRAM All electrical characteristics of netX 90 SRAM MEM-eMI part are related to C : 30 pF. For read access, device access times must match the following conditions:...
Page 55 1 or more. However, this will increase total access time by 10 ns. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 56 (1) Ready timeout. Timeout can be disabled by software. However, netX will be stalled if ready signal is permanently set to busy state. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 57: Booting And Sys Led
After a hardware reset cycle if no valid firmware image was found Note: Hardware reset means either power cycle or chip reset pin.7 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 58 Host Interface 8/16-bit DPM and SPM0/1 Ethernet xC0 PHY0, MII0, and LVDS0 Table 15: Pin configuration console modes netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 59: Alternative Boot Mode
DIP switch (or other ways). System LED The SYS LED at RDY and RUN displays the operating status of the netX 90. We recommend using a dual LED as shown in Figure 35.
Page 60: Interfaces
MMIO signals (Multiplex Matrix I/O) allow you to select and configure the interfaces you need for your application. Table 18 lists the signals possible for an MMIO pin. netX 90 offers 18 MMIOs which can be configured as follows: ...
Page 61 XC_SAMPLE0 Trigger/latch unit XC_SAMPLE1 Trigger/latch unit XC_TRIGGER0 Trigger/latch unit XC_TRIGGER 1 Trigger/latch unit Table 18: Multiplex matrix signals netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 62: Host Interface
Overview The dual-port memory (DPM) interface allows data transfer between the netX and an external host system. Unlike standard DPM, the netX 90 DPM is a virtual DPM which appears as a linear memory to the host side. The netX DPM interface can be ...
Page 63: Features
 little endian (e.g. ARM)  16-bit big endian (e.g. Motorola 16-bit CPUs)  Enhanced access error detection netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 64: Dual-Port Memory Interface Structure
 Up to 8 programmable IOs for APP CPU (PIO_APP) Note: Like all other digital I/Os of the netX 90, the DPM interface uses 3.3 V signaling voltage only. 5 V signals cannot be used! 5.2.4 Dual-port memory interface structure The internal structure of netX 90 is a synchronous design running on netX system clock (typically 100 MHz).
Page 65: Parallel Dual-Port Memory Interface
5.2.5 Parallel dual-port memory interface This section provides an overview of netX 90 parallel function and features. This includes a guide (section Parallel DPM mode and setup guide on page 68) to determine a required setting if a host CPU cannot be found in the list of Supported parallel DPM modes on page 67.
Page 66 Attention: HIF IOs used for IRQs differ for serial and parallel DPM mapping, but the IRQ function is the same. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 67 Modes are selected by configuring the function of control signals e.g. byte enables, read and write controlling or chip-selects. This leads to a wide range of supported DPM modes: The following modes are supported by netX 90 parallel DPM without any external glue logic. ...
Page 68 5.2.5.3 Parallel DPM mode and setup guide The following steps must be performed to configure the netX 90 DPM according to the host requirements. The description of register bits dpm_if_cfg provides an overview of the settings for the modes listed above. If a desired mode is not in the list, step through the following guide to determine whether the netX 90 DPM is applicable at all.
Page 69 The ready/acknowledge mode is not only an inverted version of the wait/busy mode as shown by the figures below. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 70 Z drive active high Z Figure 38: Multiplexed mode read access and ready generation (SRAM mode example) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 71 In wait/busy mode the signal does not become active then. In ready/acknowledge mode the signal becomes active state immediately at access start. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 72 Figure 41: Read data setup time and read address setup time (SRAM read) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 73 This will force the DPM to wait for a stable direction signal. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 74 Figure 42: Hazards and spikes which will be suppressed when signal filtering is enabled Note: Signal filtering cannot always eliminate all hazards, especially if overall signal quality is bad. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 75 The values are approximate values. Real timings are a little faster (about 2 ns). For exact values, see timing characteristics in section on page 88. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 76 For clearing the IRQ signal, the requesting IRQ source has to be cleared by its mask inside DPM interface. Important: IRQ signals are mapped to different netX 90 IO depending on whether serial or parallel DPM mode is selected, see section Pin table sorted by signals on page 198.
Page 77 There is no relation between endianness width and DPM interface data width. E. g. it is possible to connect a 16-bit big endian host to netX by an 8-bit DPM interconnection. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 78: Serial Dual-Port Memory Interface
In contrast to netX 51/52, the netX 90 has two serial DPMs (DPM0_SPI and DPM1_SPI) for communication between host and netX. In addition to the 4 standard SPI signals (CLK, CSN, MISO, MOSI) netX 90 has two optional interrupt signals DIRQ and SIRQ. For Quad SPI (6 lines), signals SIO2 and SIO3 signals are available.
Page 79 SPI_CLK edge has been generated before SPI_MISO change propagated to the host device. For slow clock frequencies SPI_MISO state changes a short time after the sampling clock edges. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 80 8 bits transfer end byte: 8 bits SPI_CS_N SPI_MOSI SPI_MISO Figure 45: SPI SPO=0 and SPH=1 transfer netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 81 8 bits transfer end byte: 8 bits SPI_CS_N SPI_MOSI SPI_MISO Figure 47: SPI SPO=1 and SPH=1 transfer netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 82 Data(A)[7:0] Data(A+1) D(A+length-1) will be returned. X: don’t care/undefined Figure 48: Serial DPM protocol: straight stream, type 0 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 83 5.2.6.4 Serial 4-bit DPM netX 90 DPM provides a 4-bit SPI (Quad-SPI, SQI) mode consisting of the 4 standard SPI signals plus 2 additional data lines. The way in which signal mapping is performed allows a default 1-bit SPI interconnection which can be switched to 4-bit.
Page 84 X: don’t care/undefined Figure 50: SQI Serial DPM protocol: straight stream, type 0 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 85: Handshake Registers
R/W for ARM, Read only for host (generates IRQ) (clears IRQ) netX write read Host Figure 52: Handshake cell dataflow (16-bit) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 86 The handshake cells are physically located in the internal netX memory intramhs. Intramhs (32 KB for netX 90) is dedicated to the data exchange between netX and host. Due to this, intramhs is typically mapped to external DPM address space and available for a host. The location of the 16 handshake cell pairs inside intramhs can be programmed to any 256 byte offset (bit-field base256 of register handshake_base_addr of handshake_ctrl area).
Page 87 0x100 INTRAMHS 0x0000 INTRAM8 INTRAM0 0x00000000 Figure 53: Handshake cell monitoring of intramhs netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 88: Parallel Dual-Port Memory Timing
Byte enable signals (DPM_BE signals) have address character for SRAM modes. They are treated like address lines here. Byte enables can be selected by register dpm_if_cfg.be_sel. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 89 Interfaces 89/227 5.2.8.1.1 SRAM mode read access DPM read accesses can be read or chip-select signal controlled. Moreover, netX 90 DPM supports read bursts without the necessity of read or chip-select signal toggling between each access. DPM_A, Address n Address m...
Page 90 ACHGB bus when burst addresses change. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 91 If a new external DPM write access is initiated before the internal write access is finished, external wait cycles will be inserted by setting the signal DPM_RDY. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 92 High Z Figure 58: Detailed timing of DPM SRAM mode write access when internal netX DPM side busy (insertion of wait cycles) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 93 A/D-bus). They are treated similar to the high address lines here. Byte enables can be selected by register dpm_if_cfg.be_sel. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 94 Important: If the address phase overlaps with the read active phase, the address hold time t must be shorter than the read data enable time t to avoid damage to netX or host. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 95 High Z Figure 60: Detailed timing of multiplexed SRAM mode read access with address phase overlapping into read-active phase netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 96 Figure 61: Detailed timing of multiplexed SRAM mode write access when internal netX DPM side is idle (no insertion of wait cycles) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 97 Figure 62: Detailed timing of multiplexed SRAM mode write access when internal netX DPM side busy (insertion of wait cycles) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 98 High Z Figure 63: Detailed timing of multiplexed SRAM mode write access with address phase overlapping into write-active phase netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 99 The access is terminated as soon as all byte enables have returned to inactive state. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 100 High Z Figure 65: Detailed timing of an Intel-like chip-select controlled read access with read byte enables netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 101 High Z Figure 66: Detailed timing of an Intel-like read access not using read byte enables netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 102 DPM_RDY is in acknowledge mode (ack). This is similar to normal SRAM mode (Figure 57 and Figure 58). netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 103 3 High Z drive active High Z Figure 68: Detailed timing of an Intel-like multiplexed mode read access netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 104 Figure 69: Detailed timing of an Intel-like multiplexed mode read access with address phase overlapping with read-active phase netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 105 If byte enables are ignored, the address phase could also overlap with the read-active phase. This is similar to Figure 69. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 106 SRAM mode (Figure 61 and Figure 62). Note: Also for write address phase could overlap with write-active phase. This is similar to Figure 69. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 107 Further changes of the byte enable signals will be ignored during access until they all become inactive. When all byte enables return to inactive state, access is terminated. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 108 3 High Z drive active High Z Figure 73: Detailed timing of a Motorola-like chip-select controlled read access netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 109 Write data is stored at the positive edge of RDn in this case. All other DPM input signals must be valid and stable then. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 110 3 High Z drive active High Z Figure 75: Detailed timing of a Motorola-like multiplexed mode read access netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 111 Figure 76: Detailed timing of a Motorola-like multiplexed mode read access with address phase overlapping with read- active phase netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 112 Note: Also for write address phase could overlap with the write-active phase. This is similar to Figure 76. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 113 (e.g. for power-down) by configuration registers in the netX asic_ctrl address area Configurable by register dpm_timing_cfg. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 114 That avoids problems caused by different signal runtimes if host devices simultaneously activate read enable, chip-select and address signals. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 115 It has no effect whether a 0 wait state AHB slave is shared with other system masters or not. This timing is valid for first read after 4-byte address boundary changed or for read ahead mismatch. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 116 Address phase could even overlap with the active read or write enable phase. For read, netX will never drive data lines while ALE is active even if read enable is already activated by host. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 117 Ready timing for ready signal mode 1 and drive mode 3 Symbol Parameter Type Unit Ready high-Z time RHZm13 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 118: Serial Dual-Port Memory Timing
QPM_SIO[3:0] Figure 78: DPM SPI slave timing SPO=0 and SPH=0 transfer (data valid on positive edge of serial clock) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 119 QPM_SIO[3:0] Figure 81: DPM SPI slave timing SPO=1 and SPH=1 transfer (data valid on negative edge of serial clock) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 120 (sampling and generation take place on the same clock edge). For all modes (1-bit, 4-bit, does not depend on programmable sdpm_miso_early parameter). netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 121 MISOH Figure 84: SPI timing SPO=1 and SPH=0 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 122 Figure 85: SPI timing SPO=1 and SPH=1 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK) The following values are valid for netX 90 when the module is in normal peripheral mode (not in SQIROM/ XiP mode, i.e. the enable bit of register sqi_sqirom_cfg is not set). They refer to worst case operating conditions: V : 3.0 ...
Page 123 Input filtering can be enabled/disabled in register spi_cr0/sqi_cr0 by bit filter_in. The following values are valid for netX 90 when the module is in SQIROM/XiP mode (not in normal peripheral mode, i.e. the enable bit of register sqi_sqirom_cfg is set). They refer to worst case operating conditions: V : 3.0 ...
Page 124 Figure 86: SPI slave signal timing (SPO=0 and SPH=0) Figure 87: SPI slave signal timing (SPO=0 and SPH=1) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 125 Figure 88: SPI slave signal timing (SPO=1 and SPH=0) Figure 89: SPI slave signal timing (SPO=1 and SPH=1) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 126 SMISOH instead of 2, 4, 6,… (SPH=1 modes: SPI_CLK edges 2, 4, 6,... instead of 3, 5, 6,…). netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 127: Sqi/Spi
8-bit oriented and bidirectional between master and slaves. Slave devices are selected by a chip select signal. Beside the full-duplex interface (Standard SPI), netX 90 offers a Single SPI, Dual SPI and Quad SPI interface which is half-duplex. netX 90 offers the following modes: SPI0…2_APP...
Page 128 SQI1_APP_SIO3 SQI (only): Serial input output data bit 3 signal Table 22: netX 90 – SQI/SPI signal names listed according to mode netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 129: Sqi
SPI1_APP are mapped via the multiplex matrix (see section MMIO - Multiplex Matrix on page 60. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 130 Input signal over-sampling and filtering for hazard suppression.  Static or dynamic chip-select controlling in standard SPI mode. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 131 SPI Slave 6 (Master) SPI_CS SPI_CLK SPI_MOSI SPI_MISO SPI Slave 7 SPI_CS Figure 92: Extended external SPI interconnection with DMUX netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 132 SQIROM/XiP-capable Flash device in standard SQI peripheral mode, before the SQI_XIP module can be switched to the high-performance SQIROM/XiP mode. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 133 Note: Chip-select generation can be controlled by bit fss_static of register sqi_cr1. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 134 4 to 16 bit 4 to 16 bit sqi_fss0 sqi_mosi sqi_miso Figure 96: SPI SPO=0 and SPH=1 transfer (mode 1) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 135 4 to 16 bit 4 to 16 bit sqi_fss0 sqi_mosi sqi_miso Figure 99: SPI SPO=1 and SPH=1 transfer (mode 3) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 136 6 address cycles 2 dummy cycles 2n data cycles Figure 100: SQI mode 0 and 3 transfer example netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 137 Standard SPI does not support LSB first data serialization. The configuration mode bit ms_bit_first will be ignored even in standard SPI half-duplex modes. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 138 Byte5. hi Byte5.lo Byte5.lo Figure 103: Data on the wire for data placement example of a 6-byte transfer netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 139 133 and Dual and Quad I/O interface – SQI mode on page 136) is not available when SQIROM mode is enabled. SQIROM function is available only for devices connected to chip-select signal 0. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 140 This module supports both header types controlled by bit addr_before_cmd. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 141 Reading out a 32-bit data word using XiP from address 0x1000 will deliver on HRDATA of the internal AHB interface: 0x87654321 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 142 (e.g. SST26VF016/032): a=5, d=2, i=1. An 8-bit and a 16-bit parallel Flash with 70 ns access time are also included for comparison. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 143 The serial clock IO is clamped to fix level externally or a wrong programming of the global IO configuration. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 144 Figure 110: SPI timing SPO=1 and SPH=0 transfer (data sampling on negative edge, generation on positive edge of SQI_CLK) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 145 LSB and next word MSB. Input filtering can be enabled / disabled by bit filter_in of register spi_cr0. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 146: Spi0
Interfaces 146/227 5.3.3 SPI0…2_APP and SPI_XPIC_APP netX 90 has 4 standard SPI interfaces: SPI0…2_APP and SPI_XPIC_APP. The mode is full- duplex (FIFO, Master or Slave) and can be accessed by the APP CPU only. 5.3.3.1 Features  Full master and slave functionality.
Page 147 16bit wide 16 word rdata FIFO FIFO memory controller DMA handshake DMA interface Figure 112: Block diagram of SPI module netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 148 4 to 16 bit 4 to 16 bit SPI_CSn SPI_MOSI SPI_MISO Figure 113: SPI SPO=0 and SPH=0 transfer (mode 0) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 149 4 to 16 bit 4 to 16 bit SPI_CSn SPI_MOSI SPI_MISO Figure 116: SPI SPO=1 and SPH=1 transfer (mode 3) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 150 SPI Slave 6 (master) SPI_CS SPI_CLK SPI_MOSI SPI_MISO SPI Slave 7 SPI_CS Figure 118: Extended external SPI interconnection with DMUX netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 151: Sqi0
5.3.4 SQI0…1 Apart from the full-duplex interface (Standard SPI), netX 90 offers two Quad SPI interfaces, SQI0 and SQI1. The mode is half-duplex (FIFO, Master only) and can be accessed by the APP CPU only. The SQI0…1 interface has no XiP function.
Page 152: Overview
SCL toggling without data transfers for initializing a device), an additional PIO-mode is provided. The PIO mode allows the direct programming of SDA and SCL. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 153: Block Diagram
(ASIC-internal or -external pull-up depending on the ASIC IO). In PIO mode, the output level can be driven active-high and active-low. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 154: Features
To avoid signal driving conflicts, both signals are never actively driven high. High level is realized by pad pull-up resistors. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 155: I2C Signal Conditions
2..8 START Acknowledge Acknowledge rSTART by slave by receiver or STOP Figure 121: I2C 1-byte transfer netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 156: I2C Acknowledge Handling
If a 10-bit slave device is on the I2C-bus with the appropriate MSB address bits, it will acknowledge the first byte. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 157: I2C General Call
I2C bus before it continues the SCL cycle. To escape from permanently low-tied SCL, register i2c_mcr.en_timeout can activate an SCL timeout detection. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 158: I/O Timing
500 Ohms pull-up resistor and 400 pF load. For I2C high-speed mode and high capacitive load external driver devices can be used to reach faster rise times. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 159: Multi Led
(com-side only)  com-side: 4 output pins (8 LEDs)  app-side: 8 output pins (16 LEDs) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 160: Typical Applications
Multi-LED module (com-side or app-side). netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 161: Time-Multiplexed Pwm Mode
256 + on_time[y] - 1 (on_time[y] = 255 in the example above), the output pin will switch to high-z state. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 162: Pass-Through Mode
The change will take effect at the start of the next PWM period (when the output operates in time-multiplexed PWM mode). In pass-through mode, the change will take effect immediately. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 163: Gpio
GPIO 5.6.1 Overview The netX 90 provides separate GPIO modules for com-side and app-side. The GPIO module on the com-side has 4 IO pins (GPIO11:8) and 1 counter, whereas the GPIO_APP provides 8 IO pins (GPIO7:0) and 3 counters. The main idea of the netX GPIO was to combine an IO pin with one 32-bit data register (gpio_tcX) and a counter.
Page 164 GPIO_COUNTER1 gpio_tc1 GPIO_CTRL1 gpio_counter0_ctrl gpio_counter0_max gpio_cfg0 gpio_counter0_cnt gpio_tc0 GPIO_COUNTER0 GPIO_CTRL0 Figure 131: GPIO block diagram netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 165: Features
This may be used for DC-DC PWM for assigning another GPIO pin in PWM mode to this counter. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 166: Typical Applications
The invert bit (gpio_cfgX.inv) may invert inputs and output functions. This inversion works in all modes, i.e. it is the function with the highest priority or closest to the physical pad. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 167: Counter As System Timer
As an alternative to internal GPIO counters, you can combine the global system time (sys_time) with all enhanced functionalities of GPIO pins. The global system time (a 32-bit value in ns) comes from the netX 90 SYSTIME_COM module. It is synchronized via Real-Time Ethernet according to IEEE1588.
Page 168 GPIO pin. GPIO0 SAMPLE SAMPLE SAMPLE SAMPLE gpio0_sampled gpio_cfg.mode gpio_irq_raw[0] sys_time gpio0_tc Figure 134: Capture once at rising edge netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 169: Event Counting
GPIO module. GPIO0 SAMPLE SAMPLE SAMPLE SAMPLE gpio0_sampled gpio_counter0_ctrl.run counter0_cnt Figure 136: Counting rising edges of GPIO0 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 170: Active Time Measurement
Figure 138: Watchdog mode for GPIO0 (low level should not last longer than 50 ns here) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 171: Standard Pwm
GPIO_COUNTER. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 172 In other netX chips it is not always the following GPIO. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 173: Dc-Dc Pwm
GPIO_COUNTER0 GPIO_CTRL1 GNDA GNDB gpio_cfg2 gpio_tc2 VDDB GPIO_CTRL2 Vref GPIO GNDA GNDB GNDB netX Figure 141: DC-DC PWM netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 174: Sequencer
!= "1000"). In this example the mode "set to 0" (gpio_cfgX.mode = "0100") would be a good choice. Activate the blink mode by writing gpio_cfgX.mode = "1000". This directly starts the next single sequence. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 175: Sharing Between Different Cpus
5.6.16 Interrupt handling All interrupt registers of netX (except those in some very few modules not developed by Hilscher) use the same interrupt register scheme. In this scheme, up to 32 interrupts are handled in one set of interrupt registers. A set of interrupt registers consists of two physical registers (IRQ and mask register) that are accessed by four addresses, as described in the following text: The IRQ register will store incoming interrupts until the software processes them.
Page 176: I/O Timing
Pout sample time incl. sample flip-flops SAMPLE Table 28: I/O timing parameters netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 177: Pio (Application)
Interfaces 177/227 PIO (application) The netX 90 provides several programmable input / output lines for the APP CPU. Each of the PIO signals can be used as simple input or output. Features  29 programmable input / output (application) ...
Page 178: Biss/Ssi
BiSS modules as well as the synchronization with the protocol stacks. The interrupt outputs of the BISS_CTRL modules are connected to the global interrupt logic which routes them to the ARM and xPIC CPUs of the App-side. For details, see the netX 90 interrupt documentation.
Page 179: Trigger Sources
EOT) and sets the corresponding interrupt bits in the standard netX interrupt logic. The logic consists of the following registers:  irq_raw  irq_masked  irq_msk_set  irq_msk_reset netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 180: Endat
Overview The netX 90 provides two independent EnDat 2.2 basic master modules. These EnDat modules are third party IPs customized for the netX 90. The additional logic they need is implemented in two ENDAT_CTRL modules, one for each EnDat module.
Page 181: Trigger Sources
EnDat module. For details on the requirements, see reference [8], and the description of register strobe_cfg. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 182: Can Controller
Interfaces 182/227 5.10 CAN controller On the App-side of the netX 90 there are two integrated CAN controllers. They are designed to be compatible with SJA 1000. PeliCAN mode is supported, Basic mode is not. 5.10.1 Features  SJA1000 compatibility with PeliCAN mode ...
Page 183: Uart
The UARTs on the App-side are 16550-compliant with 16 bytes transmit and receive FIFOs. They can be configured to support speeds of up to 3.125 Mbaud. In mass production netX 90 will support speeds of up to 10 Mbaud. 1 of the 3 UARTs can either be accessed by the COM or the APP-side.
Page 184 (marking state) in the idle state (the transmit encoder output has the opposite polarity to the decoder input). netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 185 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit will be set when a word is received and the previous word has not yet been read. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 186: Io-Link Controller
Interfaces 186/227 5.12 IO-Link controller netX 90 has an integrated IO-Link controller:  IO-Link V1.1  8 channels 5.12.1 Introduction IO-Link is a new communication standard interface for sensors and actuators. IO-Link allows an inexpensive point-to-point connection between sensor/actuator and the I/O assembly for the "last meter to the process".
Page 187: Typical Application
Interfaces 187/227 5.12.2 Typical application The netX 90 supports up to eight IO-Link ports. netX 90 IO-Link Master port Figure 150: netX 90 with 8 IO-Link ports Highlights of IO-Link:  Dynamical update of sensors parameters by an SPS ...
Page 188: Adc
Interfaces 188/227 5.13 ADC Figure 152 shows the four 12-bit single-ended SAR ADC units of netX 90. Each of the 4 units operates independently. V and V supply the reference voltage for the analog-to-digital SS_REF ADC_REF conversion. The selection of the reference voltage is programmable and can optionally be provided by the internal reference buffer (see electrical specification of ADC on page 197).
Page 189: Lvds
189/227 5.14 LVDS netX 90 integrates two full duplex LVDS PHYs (2 pairs of RX and 2 pairs of TX). These PHYs are intended to tunnel 100 MHz RT-Ethernet between netX chips on a backbone bus. For this purpose, Hilscher has designed its own communication protocol. It is the only protocol that can be run on these LVDS PHYs.
Page 190: Motion Pwm
To provide application support for entry-level motion / motor control one Motion PWM unit has been added. 5.16 Quadrature decoder netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 191: Ethernet Interface
Interfaces 191/227 5.17 Ethernet interface The netX 90 contains two Ethernet MACs with integrated PHYs. They support:  10Base-T / 100Base-TX  100Base-FX with external drivers  Auto-Negotiation  Auto-Crossover  Auto-Polarity They are fully compliant with IEEE 802.3 / 802.3u to run the protocols: ...
Page 192 Figure 153: Block diagram of the special real-time Ethernet features Note: For better understanding, the data switch is not shown. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 193: Fieldbus Interface
PROFIBUS DP Slave Different systems can be combined. For schematics about how to connect a fieldbus interface, see reference [2]. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 194: Debugging
Core dual Ethernet PHY 55 mA 60 mA Table 33: Current ratings for VDDIO, VDDC, PHY_VDDIO, and PHY_VDDC netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 195: Absolute Max. Ratings
0.56 W 0.62 W 0.68 W Table 34: Power consumption 7.3.1 Power consumption of netX 90 AC/DC specifications netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 196: Oscillator
Conditions Unit – V -0.3 DDIO – V -0.3 Junction temperature +125 °C Table 38: Absolute maximum ratings netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 197: Bod
Table 41: Electrical specification Note: Gain and Offset Error are measured against voltages on pins ADC_VREF and VSS_REF Failure rate (FIT) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 198: Netx 90 Package And Signal Information
90 package and signal information 198/227 8 netX 90 package and signal information Pin table sorted by signals The pin sharing options shown in the following table are prioritized: Option 1 has the lowest priority, option 9 (SDRAM) has the highest. If, e.g., you select SPI2 (peripherals) while SDRAM is selected, the SDRAM option will have priority.
Page 199 EXT_RDN IOU48S HIF_RDY DPM_RDY UART_XPIC_APP_ ETH_RXCLK EXT_RDY SD_CKE IOU48S HIF_SDCLK DPM_SIRQ UART_XPIC_APP_ XC_TRIG EXT_CS2N SD_CLK IOU48S RTSN GER0 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 200 LVDS1_TXN MII1_RXD1 / MII1_RXD1 FO1_TX XM1_TX XM1_TX_ SQI0_APP_SIO PIO_APP17 MENC_MP0 IOD48S / LVDS open / - LVDS1_TXP ECLK netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 201 (deact) ADC1_IN0 MMIO7 / MMIO7 IO_LINK1_WAKE ENDAT1_CLK BISS1_MA IOD48CS / pd (deact) ADC1_IN1 XTAL OSC_XTI OSC_XTI (XTALIN) (XTALIN) netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 202 UART_RXD UART_RXD ID24S VDDC VDDC VDD_CORE VDDC VDDC VDD_CORE VDDC VDDC VDD_CORE VDDC VDDC VDD_CORE VDDIO VDDIO VDD_IO netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 203 VSS_REF (GND) (GND) Table 42: netX 90 – Signals (pin table sorted by signals) PAD Type and power-on explanation, see section on page 212. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 204: Pin Table Sorted By Pin Number
IOU48S VDDC VDDC VDD_CORE HIF_A11 DPM_A11 SPI0_APP_CLK ETH_TXD3 EXT_A11 SD_A11 IOU48S HIF_A9 DPM_A9 GPIO6 ETH_TXD1 EXT_A9 SD_A9 IOU48S netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 205 EXT_D4 SD_D4 ID24S NK_IN LINK_IN PHY0_LED_LI PHY0_LED_ EXT_D3 SD_D3 ID24S NK_IN LINK_IN MII1_COL MII1_COL XM1_IO5 EXT_D2 SD_D2 IOD48CS netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 206 / - MII1_RXD0 / LVDS1_TXN UART_RXD UART_RXD ID24S UART_TXD UART_TXD OZD48C PHY_EXTRES PHY_EXTRE SQI_MOSI SQI_MOSI SQIROM_SIO0 IOU48S netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 207 VSS_DCDC (GND) (GND) VSS (GND) VSS (GND) COM_IO3 / GPIO11 I2C1_COM_SDA UART_CTSN MII1_TXE IOD48CS / pd (deact) ADC3_IN7 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 208 IO_LINK1_IN ENDAT1_IN BISS1_SL IOD48CS / pd (deact) ADC0_IN0 MMIO2 / MMIO2 IO_LINK0_OE ENDAT0_OE IOD48CS / pd (deact) ADC3_IN0 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 209 VDD_CORE VSS (GND) VSS (GND) Table 43: netX 90 – Pin A1 … M12 (pin table sorted by pin number) PAD Type and power-on explanation, see section on page 212. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 210: Pin Overview Netx 90
OSC_XTI OSC_XTO VDDC VSS (GND) (GND) ADC1_IN0 ADC0_IN0 ADC3_IN0 ADC2_IN0 (XTALIN) (XTALOUT) Figure 154: Pin overview netX 90 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 211 JT_TDI, JT_TDO, JT_TRST, JT_TMS, JT_TCK Power VSS (GND) VDDIO and PHY_VDDIO VDDC, VDD_PLL, PHY_VDDC Table 44: Pin overview netX 90: Colors netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 212: Pad Type Explanation
Analog ground APWR Analog power (3.3 V) VDD_CORE Core power supply (3.3 V) VDD_IO IO power supply (3.3 V) Table 45: PAD type explanation netX 90 Symbol Description pull-up resistor activated pull-down resistor activated open pull-up or pull-down resistor = deactivated...
Page 213: Schematic View Of Netx 90 Pad Types
ID24S IOD48CS IOD48S IOU48CS IOU48S IU24S OZD48C XTAL OZU48C Figure 155: Schematic view of netX 90 PAD types netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 214: Netx 90 Package
90 package and signal information 214/227 netX 90 package Figure 156: Packaging top, side, and bottom view Dimensions, see next page. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 215 0.150 Ball offset (ball): 0.080 Ball count: Edge ball center to center: 8.800 8.800 Figure 157: Packaging dimensions netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 216: Thermal Resistance
The 144-Pin BGA is compliant to the latest JEDEC J-STD-020E standard. The Moisture Sensitivity Level is MSL 3. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 217: Appendix
International Electronical Commission IEEE Institute of Electrical and Electronics Engineers Interface IO or I/O Input Output or Input/Output netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 218 UART Universal Asynchronous Receiver/Transmitter WatchDog flexible Communication (channel) XMAC (fleXible Media Access Controller) xPIC fleXible Peripheral Interface Controller netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...
Page 219: Legal Notes
The manual delivered with the product shall apply. Under no circumstances shall Hilscher Gesellschaft für Systemautomation mbH be liable for direct, indirect, ancillary or subsequent damage, or for any loss of income, which may arise after use of the information contained herein.
Page 220 Although the hardware and software was developed and tested in-depth with greatest care, Hilscher Gesellschaft für Systemautomation mbH shall not assume any guarantee for the suitability thereof for any purpose that was not confirmed in writing. No guarantee can be granted whereby...
Page 221 Hilscher Gesellschaft für Systemautomation mbH. The customer agrees to treat as confidential all of the information made available to customer by Hilscher Gesellschaft für Systemautomation mbH and rights, which were disclosed by Hilscher Gesellschaft für...
Page 222: Registered Trademarks
Sercos International e. V., Suessen, Germany. All other mentioned trademarks are property of their respective legal owners. netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 223: List Of Tables
Table 41: Electrical specification ............................. 197 Table 42: netX 90 – Signals (pin table sorted by signals) ....................203 Table 43: netX 90 – Pin A1 … M12 (pin table sorted by pin number) ................209 Table 44: Pin overview netX 90: Colors .......................... 211 Table 45: PAD type explanation netX 90.........................
Page 224: List Of Figures
Figure 10: Internal structure of the watchdog logic ......................30 Figure 11: Timing diagram of WDG_ACT.......................... 30 Figure 12: 16-bit SDRAM connection of netX 90 ....................... 36 Figure 13: Read access from different SDRAM banks ...................... 38 Figure 14: Read access from the same SDRAM banks ....................38 Figure 15: SDRAM power-up and mode register initialization ...................
Page 225 Figure 114: SPI SPO=0 and SPH=1 transfer (mode 1) ....................149 Figure 115: SPI SPO=1 and SPH=0 transfer (mode 2) ....................149 netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public...
Page 226 Figure 153: Block diagram of the special real-time Ethernet features ................192 Figure 154: Pin overview netX 90 ........................... 210 Figure 155: Schematic view of netX 90 PAD types ......................213 Figure 156: Packaging top, side, and bottom view ......................214 Figure 157: Packaging dimensions ..........................
Page 227: Contacts
Phone: +1 630-505-5301 E-Mail: info@hilscher.it E-Mail: info@hilscher.us Support Support Phone: +39 02 25007068 Phone: +1 630-505-5301 E-Mail: it.support@hilscher.com E-Mail: us.support@hilscher.com netX 90 | Technical data reference guide DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018...

hilscher netX 90 Technical Reference Manual

1 Introduction

2 General Description and Features

3 Core

4 Booting and SYS LED

5 Interfaces

7 Electrical Specification

6 Debugging

8 Netx 90 Package and Signal Information

9 Appendix

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