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UM0404
User manual
High performance ST10F276Z5 and ST10F276E
16-bit microcontrollers
Introduction
This manual describes the functionality of the ST10F276Z5 and ST10F276E devices.
An architectural overview describes the CPU performance, the on-chip system resources,
the on-chip clock generator, the on-chip peripheral blocks and the protected bits.
The operation of the CPU and the on-chip peripherals, and the different operating modes -
such as system reset, power reduction modes, interrupt handling, and system programming
- are described in individual sections.
The explanation of memory configuration has been restricted to that of the internal
addressable memory space. The ST10F276Z5 and ST10F276E Flash configurations are
not discussed in this manual. Refer to the ST10F276Z5 and ST10F276E datasheets for
detailed information (see
Appendix B: Document
references).
The Special Functional Registers are listed both by name and hexadecimal address. The
instruction set is covered in full in the ST10 Family Programming Manual and is, therefore,
not discussed in this manual. However, software programming feature - including constructs
for modularity, loops, and context switching - are described in
Section 27: System
programming on page
525.
The DC and AC electrical specifications of the device and the pin description for each
available package, are not covered in this manual but are listed in the specific device
datasheets.
Before starting on a new design, verify the device characteristics and pinout with an up-to-
date copy of the device datasheet.
The ST10F276Z5 and ST10F276E software and hardware development tools include:
• Compilers (C, C++), macro-assemblers, linkers, locators, library managers, format-
converters from Tasking & Keil
• HLL debuggers
• Real-time operating systems
• In-circuit emulators (based on Bond-out ST chips) from Hitex, Lauterbach, Nohau
• Logic analyzer disassemblers
• Evaluation boards with monitor programs from FORTH
• Industrial embedded Flash programming software from PLS
• Network driver software (CAN)
May 2013
DocID13284 Rev 2
1/564
www.st.com
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Table of Contents
Related Manuals for ST ST10F276E
Summary of Contents for ST ST10F276E
- Page 1 The explanation of memory configuration has been restricted to that of the internal addressable memory space. The ST10F276Z5 and ST10F276E Flash configurations are not discussed in this manual. Refer to the ST10F276Z5 and ST10F276E datasheets for detailed information (see Appendix B: Document references).
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Page 2: Table Of Contents
Contents UM0404 Contents Architectural overview ........22 Basic CPU concepts and optimization . - Page 3 UM0404 Contents Word, byte and bit storage ........41 On-chip Flash .
- Page 4 Contents UM0404 3.4.16 The constant zeros register ZEROS ......79 3.4.17 The constant ones register ONES ......81 Multiply-accumulate unit (MAC) .
- Page 5 UM0404 Contents Interrupt response times ........110 5.5.1 PEC response times .
- Page 6 Contents UM0404 6.7.1 Alternate functions of Port5 ....... . . 162 6.7.2 Port5 analog inputs disturb protection .
- Page 7 UM0404 Contents 8.6.1 Connecting bus masters ........204 8.6.2 Entering the hold state .
- Page 8 Contents UM0404 12.5 SSC interrupt control ........282 XBUS high-speed synchronous serial interface .
- Page 9 UM0404 Contents 15.4.6 How to compute the baud rate error ......318 15.4.7 Bootstrap via CAN ........319 15.5 Comparing the old and the new bootstrap loader .
- Page 10 Contents UM0404 17.1.1 Mode 0: standard PWM generation (edge aligned PWM) ..347 17.1.2 Mode 1: symmetrical PWM generation (center aligned PWM) ..348 17.1.3 Burst mode ..........349 17.1.4 Single shot mode .
- Page 11 UM0404 Contents 20.2 General description ........393 20.2.1 Mode selection .
- Page 12 Contents UM0404 21.9 CAN application ......... . . 444 21.9.1 Management of message objects .
- Page 13 UM0404 Contents 24.2.1 Protected power down mode ....... . 506 24.2.2 Interruptible power down mode .
- Page 14 Contents UM0404 Appendix A Abbreviations ......... . 559 Appendix B Document references .
- Page 15 UM0404 List of tables List of tables Table 1. Protected bit ............39 Table 2.
- Page 16 List of tables UM0404 Table 49. Summary of compare modes ..........337 Table 50.
- Page 17 UM0404 List of figures List of figures Figure 1. ST10F276x functional block diagram ......... 23 Figure 2.
- Page 18 List of figures UM0404 Figure 49. Port7 I/O and alternate functions ......... . . 170 Figure 50.
- Page 19 UM0404 List of figures Figure 101. Asynchronous 8-bit data frames ..........250 Figure 102.
- Page 20 List of figures UM0404 Figure 153. Operation and output waveform in mode 0........360 Figure 154.
- Page 21 UM0404 List of figures Figure 205. Minimum external reset circuitry ..........491 Figure 206.
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Page 22: Architectural Overview
Architectural overview UM0404 Architectural overview ST10F276 architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the ST10F276 (see Figure Basic CPU concepts and optimization... -
Page 23: Figure 1. St10F276X Functional Block Diagram
UM0404 Architectural overview Figure 1. ST10F276x functional block diagram XFLASH IFLASH 512K CPU-Core and MAC Unit 320K IRAM XRAM XRTC Watchdog XRAM Oscillator (STBY) 32 kHz Oscillator XPWM XRAM Interrupt Controller XASC (PEC) 5V-1.8V XI2C XSSC Voltage Regulator XCAN1 XCAN2 Port 6 Port 5 Port 3... -
Page 24: High Instruction Bandwidth / Fast Execution
Architectural overview UM0404 Figure 2. CPU block diagram 2 Kbyte IRAM STKOV STKUN Multiplication Division Hardware Bank n 512 Kbyte IFlash General Bit-Mask Purpose Generator Execution Unit Registers Instruction Pointer 4-Stage Pipeline 16-bit Barrel-Shift Bank i SYSCON BUSCON 0 320 Kbyte XFlash BUSCON 1 ADDRSEL 1... -
Page 25: High Function 8-Bit And 16-Bit Alu
UM0404 Architectural overview 1.1.2 High function 8-bit and 16-bit ALU All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, the condition flags for byte operations are provided from the sixth and seventh bit of the ALU result. -
Page 26: Consistent And Optimized Instruction Formats
Architectural overview UM0404 To decrease loop execution overhead, three enhancements have been provided: Single cycle branch execution is provided after the first iteration of a loop. Therefore, only one instruction cycle is lost during the execution of the entire loop. In loops which fall through upon completion, no instruction cycle is lost when exiting the loop. -
Page 27: Programmable Multiple Priority Interrupt System
UM0404 Architectural overview specify the required operands. 1.1.6 Programmable multiple priority interrupt system The following enhancements have been included to allow processing of a large number of interrupt sources: • Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU. -
Page 28: Peripheral Event Control And Interrupt Control
Architectural overview UM0404 1.2.1 Peripheral event control and interrupt control The Peripheral Event Controller (PEC) makes it possible to respond to an interrupt request with a single data transfer (word or byte) which only consumes one instruction cycle and does not require a save and restore of the machine status. Each interrupt source is prioritized in every instruction cycle in the interrupt control block. -
Page 29: External Bus Interface
UM0404 Architectural overview external RAM. Therefore it cannot store register banks and is not bit addressable. The XRAM allows 16-bit accesses with maximum speed. A portion of the on-chip XRAM (16 Kbytes) represents the Stand-by RAM, which can be maintained biased through EA/V STBY pin when main supply V is turned off. -
Page 30: Clock Generator
Architectural overview UM0404 The on-chip XRAM and XFlash, the on-chip CAN-Modules, the XASC, the XSSC, the XPWM, the I C interface, the RTC are all examples for these X-Peripherals. Clock generator The on-chip clock generator provides the ST10F276 with its basic clock signal that controls the activities of the controller hardware. -
Page 31: Pll Operation
UM0404 Architectural overview 1.3.1 PLL operation The PLL is enabled except when P0H.[7..5] = ‘011’ or ‘001’ during reset (Direct Drive and Prescaler modes). At Power-On, the PLL provides a stable clock signal in less than 1ms after V has reached 5V±10%, even if there is no external clock signal (in this case, the PLL will run on its basic frequency of 750 kHz to 3 MHz). -
Page 32: Oscillator Watchdog (Owd)
Architectural overview UM0404 1.3.4 Oscillator watchdog (OWD) In order to provide a fail safe mechanism for the instance of a loss of the external clock, an oscillator watchdog is implemented when the selected clock option is direct drive or direct drive with prescaler. -
Page 33: Peripheral Interfaces
UM0404 Architectural overview In order to enhance the performance of the device, a set of additional on-chip X-Peripherals are available on ST10F276 and controlled through dedicated set of registers: • Two CAN interfaces, • Two additional Serial Interfaces (XASC and XSSC), •... -
Page 34: Parallel Ports
Architectural overview UM0404 Byte write operations to word wide SFRs via indirect or direct 16-bit (mem) addressing or byte transfers via the PEC, force zeros in the non-addressed byte. Byte write operations via short 8-bit (reg) addressing can only access the low byte of an SFR and force zeros in the high byte. -
Page 35: General Purpose Timer (Gpt) Unit
UM0404 Architectural overview Asynchronous/Synchronous Serial Channels (ASC0 and XASC) and two High-Speed Synchronous Serial Channels (SSC and XSSC). They support full-duplex asynchronous communication and half-duplex synchronous communication. The SSC may be configured so it interfaces with serially linked peripheral components. Two dedicated Baud rate generators allow to set up all standard Baud rates without oscillator tuning. -
Page 36: Watchdog Timer
Architectural overview UM0404 The core timers T3 and T6 have output toggle latches (TxOTL) which change their state on each timer overflow / underflow. The state of these latches may be output on port pins (TxOUT) or may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32/33-bit timers/counters for measuring long time periods with high resolution. -
Page 37: Pulse Width Modulation Unit
UM0404 Architectural overview In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. -
Page 38: Can Module
Architectural overview UM0404 In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without the overhead of interrupt routines for each data transfer. -
Page 39: Protected Bits
UM0404 Architectural overview Protected bits The ST10F276x MCU provides up to 106 protected bits. These bits are modified by the on- chip hardware during special events such as Power-On reset, power failure, or application hardware. These bits cannot be modified by some wrong software accesses. Table 1. -
Page 40: Memory Organization
Memory organization UM0404 Memory organization The memory space of the ST10F276 is organized as a unified memory. Code memory, data memory, registers and I/O ports are organized within the same linear address space. All of the physically separated memory areas, including on-chip IFlash, IRAM, the internal Special Function Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals and external memory are mapped into one common address space. -
Page 41: Word, Byte And Bit Storage
UM0404 Memory organization Figure 4. ST10F276 memory mapping (user mode: Flash Read operation) Code Data Data Code Page Page Segment Segment FF FFFF 1023 11 FFFF Ext. Memory 00 FFFF 11 0000 00 FE00 10 FFFF 00 FDFF Ext. Memory 10 0000 0F FFFF IRAM... -
Page 42: On-Chip Flash
Memory organization UM0404 Double words (code only) are stored in ascending memory locations as two subsequent words. Single bit are always stored in the specified bit position at a word address. Bit position 0 is the least significant bit of the byte at an even byte address, and bit position 15 is the most significant bit of the byte at the next odd byte address. -
Page 43: Table 2. Segment 8 Address Range Mapping
UM0404 Memory organization Table 2. Segment 8 address range mapping ROMEN XPEN XRAM2EN XFLASHEN Segment 8 External Memory External Memory Reserved Reserved IFlash (B1F1) Note: The symbol ‘x’ in the table above stands for ‘do not care’. Table 3. 512 Kbyte IFlash memory block organization Addresses Addresses Block... -
Page 44: Iram And Sfr Area
Memory organization UM0404 Code fetches are always made on even byte addresses. The last valid code location must contain a branch instruction (unconditional), because sequential boundary crossing from internal Flash to external memory is not supported and causes erroneous results. Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. -
Page 45: Figure 6. On-Chip Ram And Sfr/Esfr Areas
UM0404 Memory organization Figure 6. On-chip RAM and SFR/ESFR areas Code Data Data Code Page Page RAM / SFR (4Kbyte) Segment Segment FF FFFF 1023 11 FFFF Ext. Memory 01 0000 00 FFFF 00 FFFF 11 0000 00 FE00 10 FFFF 00 FDFF 00 FE00 Ext. -
Page 46: System Stack
Memory organization UM0404 The upper 256 bytes of the IRAM (00’FD00h through 00’FDFFh) and the GPRs of the current bank are provided for single bit storage, and therefore, they are bit addressable (see Figure 1 on page 23). 2.3.1 System stack The system stack may be defined within the IRAM. -
Page 47: Pec Source And Destination Pointers
UM0404 Memory organization Context Pointer register (CP) is active at a given time. Selecting a new active register bank is simply done by updating the CP register. A particular Switch Context (SCXT) instruction performs register bank switching and an automatic saving of the previous context. The number of implemented register banks (arbitrary sizes) is only limited by the size of the available IRAM. -
Page 48: Special Function Registers
Memory organization UM0404 Figure 7. Location of the PEC pointers 00’FD00h 00’FCFEh DSTP7 00’FCFEh 00’FCFCh SRCP7 00’FCE0h 00’FCDEh Internal source & destination pointers DSTP0 00’FCE2h 00’F600h 00’F5FEh 00’FCE0h SRCP0 2.3.4 Special function registers The functions of the CPU, the bus interface, the I/O ports and the on-chip peripherals of the ST10F276 are controlled via a number of so-called Special Function Registers (SFRs). -
Page 49: The On-Chip Xram
UM0404 Memory organization ;This instruction uses 16-bit address to access ;ESFR T8REL. R1 is duplicated and also ;accessible via T8REL, R1 the ESFR mode ;(EXTR is not required for this access) ;----- ;------ ;The scope of the EXTR #3 instruction ends here! ;This instruction uses 16-bit address, and does T8REL, R1 ;not require switching... -
Page 50: Xram Access Via External Masters
Memory organization UM0404 Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. There is no short addressing mode for XRAM operands. Any word data access is made to an even byte address. For PEC data transfers XRAM1 can be accessed independently of the contents of the DPP registers, via the PEC source and destination pointers. -
Page 51: Crossing Memory Boundaries
UM0404 Memory organization The ST10F276 also supports four different bus types: • Multiplexed 16-bit Bus with address and data on PORT0 (Default after Reset) • Multiplexed 8-bit Bus with address and data on PORT0 (P0L) • De-multiplexed 16-bit Bus with address on PORT1 and data on PORT0 •... -
Page 52: The Central Processing Unit (Cpu)
The central processing unit (CPU) UM0404 The central processing unit (CPU) The CPU is used to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated results. - Page 53 UM0404 The central processing unit (CPU) Beside its normal operation there are the following particular CPU states: • RESET state: Any reset (hardware, software, watchdog) forces the CPU into a pre- defined active state. • IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the on-chip peripherals keep running.
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Page 54: Instruction Pipelines
The central processing unit (CPU) UM0404 Figure 8. CPU block diagram 2 Kbyte IRAM STKOV STKUN Multiplication Division Hardware Bank n 512 Kbyte General IFlash Bit-Mask Purpose Generator Execution Unit Registers Instruction Pointer 4-Stage Pipeline 16-bit Barrel-Shift Bank i SYSCON BUSCON 0 320 Kbyte XFlash... -
Page 55: Sequential Instruction Processing
UM0404 The central processing unit (CPU) • Write back: All external operands and the remaining operands within the IRAM space are written back. Injected instructions are generated internally by the machine to provide extra time for instructions that require more than one instruction cycle. Instructions are automatically injected into the decode stage of the pipeline, they pass through the remaining stages like every standard instruction. -
Page 56: Cache Jump Instruction Processing
The central processing unit (CPU) UM0404 Figure 10. Standard branch instruction pipelining Injection 1 instruction cycle FETCH BRANCH TARGET TARGET+1 TARGET+2 TARGET+3 DECODE BRANCH INJECT TARGET TARGET+1 TARGET+2 EXECUTE . . . BRANCH INJECT TARGET TARGET+1 WRITEBACK .. - Page 57 UM0404 The central processing unit (CPU) This prevents delays that would cause the pipeline to become noticeable to the user. However, there are some cases where allowances must be made by the programmer, for the pipeline architecture of the ST10F276. In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance.
- Page 58 The central processing unit (CPU) UM0404 External memory access sequences The effect described here will only become noticeable, when watching the external memory access sequences on the external bus by means of a Logic Analyzer. Different pipeline stages can simultaneously put a request on the External Bus Controller (EBC). The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC, due to the predefined priority of external memory accesses.
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Page 59: Bit-Handling And Bit-Protection
UM0404 The central processing unit (CPU) ; any instruction not accessing Port3 BSET P3.5 ; P3.13 is now output, ; the read-modify-write reads the P3.13 output ; latch Changing the system configuration The instruction following an instruction that changes the system configuration via register SYSCON (like the mapping of the internal memory, like segmentation, like stack size), cannot use the new resources (Memory or stack). -
Page 60: Instruction Execution Times
The central processing unit (CPU) UM0404 All instructions that change single bit or bit groups internally use a read-modify-write sequence that accesses the whole word containing the specified bit(s). This method has several consequences: • Bit can only be modified within the internal specific address areas (IRAM, SFRs...). External locations cannot be used with bit instructions. -
Page 61: Cpu Special Function Registers
UM0404 The central processing unit (CPU) programming of the bus cycles (wait-states). The operand and instruction accesses listed below can extend the execution time of an instruction: • Internal IFlash Memory operand reads (same for byte and word operand reads), •... -
Page 62: The System Configuration Register Syscon
The central processing unit (CPU) UM0404 Note: Note that any explicit write request (via software) to an SFR supersedes a simultaneous modification of the same register, by hardware. Any write operation to a single byte of an SFR clears the non-addressed complementary byte within the specified SFR. - Page 63 UM0404 The central processing unit (CPU) Function Power Down Mode Configuration Control ‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. To exit Power Down Mode, an external reset must occur by asserting the RSTIN pin. PWDCFG ‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive...
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Page 64: Table 8. Stack Size
The central processing unit (CPU) UM0404 programmed prescaled value of the f (prescaler factor is programmable from 1 to 256 linearly, default value after reset is 1). Note: The output driver of port pin P3.15 is switched on automatically, when the CLKOUT function is enabled. -
Page 65: X-Peripherals Control Register (Xpercon)
UM0404 The central processing unit (CPU) 3.4.2 X-Peripherals control register (XPERCON) XPERCON (F024h / 12h) ESFR Reset Value: - 005h XMISC XI2C XSSC XASC XPWM XFLAS XRTC XRAM2 XRAM1 CAN2 CAN1 Function CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5 and P4.6 pins can be used as general purpose IOs, but address range 00’EF00h- CAN1EN 00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,... -
Page 66: Xpercon And Xperemu Registers
The central processing unit (CPU) UM0404 Function XASC Enable Bit ‘0’: Accesses to the on-chip XASC are disabled, external access performed. Address XASCEN range 00’E900h-00’E9FFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also. ‘1’: The on-chip XASC is enabled and can be accessed. -
Page 67: Emulation Dedicated Registers
UM0404 The central processing unit (CPU) introduced on XBUS for the new ST10 generation. The following instructions must be added inside the initialization routine: if (SYSCON.XPEN && (XPERCON & 0x07D3)) then { XPEREMU = XPERCON } Of course, XPEREMU must be programmed after XPERCON and after SYSCON, in such a way the final configuration for X-Peripherals is stored in XPEREMU and used for the emulation hardware setup. - Page 68 The central processing unit (CPU) UM0404 PSW (FF10h / 88h) Reset Value: 0000h ILVL USR0 Function Negative Result Set when the result of an ALU operation is negative. Carry Flag Set when the result of an ALU operation produces a carry bit. Overflow Result Set when the result of an ALU operation produces an overflow.
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Page 69: Table 9. Shift Right Rounding Error Evaluation
UM0404 The central processing unit (CPU) operand the N-flag represents the previous state of the specified bit. For Boolean bit operations with two operands the N-flag represents the logical XOR of the two specified bits. C-Flag: After an addition the C-flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated. -
Page 70: The Instruction Pointer Ip
The central processing unit (CPU) UM0404 flag represents the logical NORing of the two specified bits. For the prioritize ALU operation the Z-flag indicates, if the second operand was zero or not. E-Flag: The E-flag can be altered by instructions, which perform ALU or data movement operations. -
Page 71: The Code Segment Pointer Csp
UM0404 The central processing unit (CPU) Function Instruction Pointer Specifies the intra segment offset, from where the current instruction is to be fetched. IP refers to the current segment (SEGNR bit field of CSP register). 3.4.7 The code segment pointer CSP This non-bit-addressable register selects the code segment being used at run-time to access instructions. -
Page 72: The Data Page Pointers Dpp0, Dpp1, Dpp2, Dpp3
The central processing unit (CPU) UM0404 The CSP register can only be read but not written by data operations. It is, however, modified either directly by means of the JMPS and CALLS instructions, or indirectly via the stack by means of the RETS and RETI instructions. Upon the acceptance of an interrupt or the execution of a software TRAP instruction, the CSP register is automatically set to zero. -
Page 73: The Context Pointer Cp
UM0404 The central processing unit (CPU) Data paging is performed by concatenating the lower 14 bits of an indirect or direct, long 16 bit address with the contents of the DPP register, selected by the upper two bits of the 16-bit address. - Page 74 The central processing unit (CPU) UM0404 CP (FE10h / 08h) Reset Value:FC00h Function Modifiable portion of register CP Specifies the (word) base address of the current register bank. When writing a value to register CP with bit CP.11...CP.9 = ‘000’, bit CP.11...CP.10 are set to ‘11’ by hardware, in all other cases all bits of bit-field “CP”...
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Page 75: Figure 14. Register Bank Selection Via Register Cp
UM0404 The central processing unit (CPU) Figure 14. Register bank selection via register CP IRAM (CP) + 30 (CP) + 28 Context Pointer (CP) + 2 (CP) Figure 15. Implicit CP use by short GPR addressing modes Specified by register or bitoff Context Pointer 1111 4-bit GPR Address... -
Page 76: The Stack Pointer Sp
The central processing unit (CPU) UM0404 3.4.10 The stack pointer SP This non-bit-addressable register is used to point to the top of the internal system stack (TOS). The SP register is pre-decremented whenever data is to be pushed onto the stack, and it is post-incremented whenever data is to be popped from the stack. -
Page 77: The Stack Underflow Pointer Stkun
UM0404 The central processing unit (CPU) Fatal error indication treats the stack overflow as a system error through the associated trap service routine. Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap. Automatic system stack flushing allows to use the system stack as a 'Stack Cache' for a bigger external user stack. -
Page 78: The Multiply / Divide High Register Mdh
The central processing unit (CPU) UM0404 This control mechanism is not triggered, and no stack trap is generated, when: • The stack pointer SP is directly updated via MOV instructions. • The limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the new limits. -
Page 79: The Multiply / Divide Control Register Mdc
UM0404 The central processing unit (CPU) Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. The MDRIU flag is cleared, whenever the MDL register is read via software. When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, register MDL must be saved along with registers MDH and MDC to avoid erroneous results. - Page 80 The central processing unit (CPU) UM0404 manipulation or mask generation. It can be accessed via any instruction which is capable of addressing an SFR. ZEROS (FF1Ch / 8Eh) Reset Value: 0000h 80/564 DocID13284 Rev 2...
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Page 81: The Constant Ones Register Ones
UM0404 The central processing unit (CPU) 3.4.17 The constant ones register ONES All bits of this bit-addressable register are fixed to '1' by hardware. This register is read only. Register ONES can be used as a register-addressable constant of all ones, for bit manipulation or mask generation. -
Page 82: Multiply-Accumulate Unit (Mac)
Multiply-accumulate unit (MAC) UM0404 Multiply-accumulate unit (MAC) The MAC is a specialized co-processor added to the ST10F276 CPU core to improve the performance of signal processing algorithms. It includes: • A multiply-accumulate unit. • An address generation unit, able to feed the MAC unit with 2 operands per cycle. •... -
Page 83: Mac Operation
UM0404 Multiply-accumulate unit (MAC) Program control • Repeat Unit allowing some MAC co-processor instructions to be repeated up to 8192 times. Repeated instructions may be interrupted. • MAC interrupt (Class B Trap) on MAC condition flags. MAC operation Figure 16. MAC architecture Operand 1 Operand 2 (MA-bus) -
Page 84: Instruction Pipelining
Multiply-accumulate unit (MAC) UM0404 4.2.1 Instruction pipelining All MAC instructions use the 4-stage pipeline. During each stage the following tasks are performed: • FETCH: All new instructions are double-word instructions. • DECODE: If required, operand addresses are calculated and the resulting operands are fetched. -
Page 85: Address Generation
UM0404 Multiply-accumulate unit (MAC) Code MSW (before) MSW (after) Comment MOV MSW, #0 0000h MOV R0, #0 CoADD R0, R0 0000h 0200h MSW.Z set at execute BFLDL MSW, #FFh, #FFh 0200h 00FFh Error! In this example, the BFLDL instruction performs a read access to the MSW during the decode stage while the MSW.Z flag is only set at the end of the execute stage of the CoADD. -
Page 86: 16 X 16 Signed/Unsigned Parallel Multiplier
Multiply-accumulate unit (MAC) UM0404 the post-modification of IDX . It is obtained by the reverse operation than the one used to calculate the new value of IDX . The following table shows these rules. Table 11. Parallel data move addressing Instruction Writeback address +],... -
Page 87: The 40-Bit Signed Accumulator Register
UM0404 Multiply-accumulate unit (MAC) concatenation of MA- and MB-buses. Product and Concatenation can be shifted left by one according to MP for the multiplier or to the instruction for the concatenation. The B-input port is fed either by the 40-bit shifted/not shifted and inverted/not inverted accumulator or by 00’0000’0000h. -
Page 88: The 40-Bit Adder / Subtracter
Multiply-accumulate unit (MAC) UM0404 POP MAL POP MSW 4.2.7 The 40-bit adder / subtracter The 40-bit Adder/Subtracter allows intermediate overflows in a series of multiply/accumulate operations. The Adder/Subtracter has two input ports. One input is the feedback of the 40- bit Signed Accumulator output through the ACCU-Shifter. -
Page 89: The Accumulator Shifter
UM0404 Multiply-accumulate unit (MAC) 4.2.9 The accumulator shifter The accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The source accumulator shifting operations are: • No shift (Unmodified) • Up to 8-bit Arithmetic Left Shift •... -
Page 90: Mac Interrupt
Multiply-accumulate unit (MAC) UM0404 the interrupt routine, MRW must be saved by the user and restored before the end of the interrupt routine. Note: The Repeat Count should be used with caution. In this case MR should be written as 0. In general MR should not be set by the user otherwise correct instruction processing cannot be guaranteed. -
Page 91: Mac Register Set
UM0404 Multiply-accumulate unit (MAC) The MAC implements ‘2’s complement rounding’. With this rounding type, one is added to the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared). MAC register set 4.3.1 Address registers The new addressing modes require new (E)SFRs: Two address pointers IDX0 / IDX1 and four offset registers QX0 / QX1 and QR0 / QR1. - Page 92 Multiply-accumulate unit (MAC) UM0404 Function MAC Unit Accumulator High (bits [31...16]) MAL (FE5Ch / 2Eh) Reset Value: 0000h Function MAC Unit Accumulator Low (bits [15...0]) MSW (FFDEh / EFh) Reset Value: 0200h Function Accumulator Extension (bits [39:32]) Negative Flag Set when the Accumulator is negative at the end of a MAC operation. Zero Flag Set when the Accumulator is zero at the end of a MAC operation.
- Page 93 UM0404 Multiply-accumulate unit (MAC) MCW (FFDCh / EEh) Reset Value: 0000h Function Saturation Mode When set, enables automatic 32-bit saturation of the result of a MAC operation. Product Shift Mode When set, enables the one-bit left shift of the multiplier output in case of a signed- signed multiplication.
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Page 94: Mac Instruction Set Summary
Multiply-accumulate unit (MAC) UM0404 Table 13. MAC register address in CoReg addressing mode Registers Description Address MAC-Unit Status Word 00000b MAC-Unit Accumulator High 00001b “limited” MAH /signed 00010b MAC-Unit Accumulator Low 00100b MAC-Unit Control Word 00101b MAC-Unit Repeat Word 00110b MAC instruction set summary The following table gives an overview of the MAC instruction set. - Page 95 UM0404 Multiply-accumulate unit (MAC) Table 14. MAC instruction set summary (continued) Mnemonic Addressing modes Repeatable , Rw CoLOAD( 2, -) ⊗], [Rw ⊗] [IDX CoCMP ⊗] , [Rw CoSHL CoSHR #data4 CoASHR ⊗] CoASHR, rnd , Rw CoABS ⊗], [Rw ⊗] [IDX ⊗]...
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Page 96: Interrupt And Trap Functions
Interrupt and trap functions UM0404 Interrupt and trap functions The architecture of the ST10F276 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. These mechanisms include: •... -
Page 97: Table 15. Interrupt And Pec Service Request Sources
UM0404 Interrupt and trap functions The ST10F276 provides a vectored interrupt system. In this system specific vector locations in the memory space are reserved for the reset, trap, and interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated with the respective interrupt source. - Page 98 Interrupt and trap functions UM0404 Table 15. Interrupt and PEC service request sources (continued) Source of interrupt or Request Enable Interrupt Vector Trap PEC service request flag flag vector location number CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h CAPCOM Register 14 CC14IR CC14IE CC14INT...
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Page 99: Table 16. Vector Locations And Status For Hardware Traps
UM0404 Interrupt and trap functions Table 15. Interrupt and PEC service request sources (continued) Source of interrupt or Request Enable Interrupt Vector Trap PEC service request flag flag vector location number ASC0 Error S0EIR S0EIE S0EINT 00’00B0h SSC Transmit SSCTIR SSCTIE SSCTINT 00’00B4h... -
Page 100: Normal Interrupt Processing And Pec Service
Interrupt and trap functions UM0404 Reset conditions have priority over every other system activity and therefore have the highest priority (trap priority III). Software traps may be initiated to any vector location between 00’0000h and 00’01FCh. A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit-field ILVL in register PSW. -
Page 101: Interrupt Priority Level And Group Level
UM0404 Interrupt and trap functions Function Group Level Defines the internal order for simultaneous requests of the same priority. GLVL ’3h’: Highest group priority ’0h’: Lowest group priority Interrupt Priority Level Defines the priority level for the arbitration of requests. ILVL ’Fh’: Highest priority level ’0h’: Lowest priority level... -
Page 102: Figure 19. Priority Levels And Pec Channels
Interrupt and trap functions UM0404 Note: Priority level 0000b is the default level of the CPU. Therefore a request on level 0 will never be serviced, because it can never interrupt the CPU. However, an enabled interrupt request on level 0000b will terminate the ST10F276’s Idle mode and reactivate the CPU. For interrupt requests which are to be serviced by the PEC, the associated PEC channel number is derived from the respective ILVL (LSB) and GLVL (see Figure... -
Page 103: Interrupt Control Functions In The Psw
UM0404 Interrupt and trap functions Note: All requests on levels 13...1 cannot initiate PEC transfers. They are always serviced by an interrupt service routine. No PECC register is associated and no COUNT field is checked. 5.1.5 Interrupt control functions in the PSW The Processor Status word (PSW) is functionally divided into two parts: The lower byte of the PSW basically represents the arithmetic status of the CPU, the upper byte of the PSW controls the interrupt system of the ST10F276 and the arbitration mechanism for the... -
Page 104: Operation Of The Pec Channels
Interrupt and trap functions UM0404 Hardware traps switch the CPU level to maximum priority (15) so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed. Note: The TRAP instruction does not change the CPU level, so software invoked trap service routines may be interrupted by higher requests. - Page 105 UM0404 Interrupt and trap functions Byte/word transfer bit BWT controls if a byte or a word is moved during a PEC service cycle. This selection controls the transferred data size and the increment step for the modified pointer. Increment control field INC controls if one of the PEC pointers is incremented after the PEC transfer.
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Page 106: Prioritizing Interrupt & Pec Service Requests
Interrupt and trap functions UM0404 The source and destination pointers specify the locations between which the data is to be moved. A pair of pointers (SRCPx and DSTPx) is associated with each of the eight PEC channels. These pointers do not reside in specific SFRs, but are mapped into the IRAM of the ST10F276 just below the bit-addressable area (see Figure 20). -
Page 107: Interrupt Class Management
UM0404 Interrupt and trap functions serviced. If its level is higher than the current CPU level. Changing the CPU level to a specific value via software blocks all requests on the same or a lower level. An interrupt source that is assigned to level 0 will be disabled and never be serviced. •... -
Page 108: Saving The Status During Interrupt Service
Interrupt and trap functions UM0404 Table 18. Example of software controlled interrupt classes GLVL ILVL (priority) Interpretation Interrupt Class 3: 6 sources on 2 levels No service! Saving the status during interrupt service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. -
Page 109: Context Switching
UM0404 Interrupt and trap functions Figure 21. Task status saved on the system stack High Status of Addresses Interrupted Task Addresses a) System stack before b) System stack after b) System stack after Interrupt Entry Interrupt Entry (unsegmented) Interrupt Entry (segmented) The interrupt request flag of the source that is being serviced is cleared. -
Page 110: Interrupt Response Times
Interrupt and trap functions UM0404 Interrupt response times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction (I1) being fetched from the interrupt vector location. The basic interrupt response time for the ST10F276 is three instruction cycles (see Figure 22). -
Page 111: Pec Response Times
UM0404 Interrupt and trap functions In case instruction N reads the PSW and instruction N-1 has an effect on the condition flags, the interrupt response time may additionally be extended by two CPU clock cycles. The worst case interrupt response time during internal Flash program execution adds to 12 CPU clock cycles. -
Page 112: Figure 23. Pipeline Diagram For Pec Response Time
Interrupt and trap functions UM0404 Figure 23. Pipeline diagram for PEC response time Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N + 1 N + 2 N + 2 DECODE N - 1 N + 1 EXECUTE N - 2 N - 1... -
Page 113: External Interrupts
UM0404 Interrupt and trap functions Depending on where the instructions, source and destination operands are located, there is a number of combinations. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: • The worst case PEC response time including external accesses will occur, when instructions N and N+1 are executed out of external memory, instructions N-1 and N require external operand read accesses and instructions N-3, N-2 and N-1 write back external operands. -
Page 114: Table 19. Pins To Be Used As External Interrupt Inputs
Interrupt and trap functions UM0404 into capture register CCx, independent whether the timer is running or not. When the interrupt enable bit CCxIE is set, a PEC request or an interrupt request for vector CCxINT will be generated (see Table 19). -
Page 115: Fast External Interrupts
UM0404 Interrupt and trap functions 5.6.1 Fast external interrupts The input pins that may be used for external interrupts are sampled every eight CPU clock cycles: This means that the external events are scanned and detected in timeframes of eight CPU clock cycles. The ST10F276 provides eight interrupt inputs that are sampled every CPU clock cycle so external events are captured faster than with standard interrupt inputs. - Page 116 Interrupt and trap functions UM0404 Note: The I C interface implements an input analog filter to avoid that spurious spikes are taken into account as valid bus transitions. For this reason, a pulse on the SCL line should be long enough to be recognized as valid pulse: this is in the range of 500ns (minimum).
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Page 117: X-Peripheral Interrupt
UM0404 Interrupt and trap functions CANPAR XI2CEN CAN2EN CAN1EN Interrupt P4.5 Interrupt P4.4 Yes (CAN1) Yes (CAN2) Yes (CAN1) Yes (CAN2) Yes (CAN1/2) Yes (I Yes (CAN1) Yes (I Yes (I Yes (CAN1) Yes (I Yes (CAN1/2) Yes (I EXxIN inputs are normally sampled interrupt inputs. However, the interrupt handler circuitry uses them as level-sensitive inputs. -
Page 118: Table 20. X-Interrupt Detailed Mapping
Interrupt and trap functions UM0404 absence of the possibility to serve the related interrupt request: a periodic polling of the flag bits may be implemented inside the user application. Note: The XIRxSEL registers are mapped into the XMiscellaneous area. Therefore they can be accessed only if the XMISCEN bit is set in XPERCON register and if XPEN bit is set in SYSCON register. - Page 119 UM0404 Interrupt and trap functions Table 20. X-Interrupt detailed mapping XP0INT XP1INT XP2INT XP3INT XASC Receive XASC Transmit XASC Transmit Buffer XASC Error PLL Unlock / OWD PWM1 Channel 3...0 XIR0SEL (EB10h) XBUS Reset Value: 0000h IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 FL.7 FL.6 FL.5 FL.4 FL.3 FL.2 FL.1 FL.0 Function Interrupt Flag 0: CAN1 Interrupt FL.0...
- Page 120 Interrupt and trap functions UM0404 Function Interrupt Enable 1: I2C Transmit IE.1 ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. Interrupt Enable 2: I2C Receive IE.2 ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. Interrupt Enable 3: XSSC Transmit IE.3 ‘0’: Interrupt request disabled.
- Page 121 UM0404 Interrupt and trap functions XIR0CLR (EB14h) XBUS Reset Value: 0000h IECLR[7:0] FLCLR[7:0] Function Interrupt Flag x CLEAR (x=7...0) FLCLR.x Writing a ‘1’ will clear the corresponding bit x in XIR0SEL register. Writing a ‘0’ has no effect. Interrupt Enable x CLEAR (x=7...0) IECLR.x Writing a ‘1’...
- Page 122 Interrupt and trap functions UM0404 Function Interrupt Flag 4: XSSC Receive FL.4 ‘0’: No interrupt request. ‘1’: Interrupt request pending. Interrupt Flag 5: XASC Transmit Buffer FL.5 ‘0’: No interrupt request. ‘1’: Interrupt request pending. Interrupt Flag 6: XASC Transmit FL.6 ‘0’: No interrupt request.
- Page 123 UM0404 Interrupt and trap functions XIR1SET (EB22h) XBUS Reset Value: 0000h IESET[7:0] FLSET[7:0] Function Interrupt Flag x SET (x=7...0) FLSET.x Writing a ‘1’ will set the corresponding bit x in XIR1SEL register. Writing a ‘0’ has no effect. Interrupt Enable x SET (x=7...0) IESET.x Writing a ‘1’...
- Page 124 Interrupt and trap functions UM0404 Function Interrupt Flag 0: XPWM Channel 3...0 FL.0 ‘0’: No interrupt request. ‘1’: Interrupt request pending. Interrupt Flag 1: I2C Transmit FL.1 ‘0’: No interrupt request. ‘1’: Interrupt request pending. Interrupt Flag 2: I2C Receive FL.2 ‘0’: No interrupt request.
- Page 125 UM0404 Interrupt and trap functions Function Interrupt Enable 6: XASC Transmit IE.6 ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. Interrupt Enable 7: XASC Receive IE.7 ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. All bits of XIR2SEL register are set by hardware when an interrupt is coming from the peripheral, and/or by writing a logic ‘1’...
- Page 126 Interrupt and trap functions UM0404 XP2IC (F196h / CBh) ESFR Reset Value: - - 00h XP2IR XP2IE ILVL GLVL Note: Refer to Section 5.1.3: Interrupt control registers on page 100 for an explanation of the control fields. XIR3SEL (EB40h) XBUS Reset Value: 0000h IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 FL.7 FL.6 FL.5 FL.4 FL.3 FL.2 FL.1 FL.0 Function...
- Page 127 UM0404 Interrupt and trap functions Function Interrupt Enable 3: XSSC Error IE.3 ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. Interrupt Enable 4: XASC Error IE.4 ‘0’: Interrupt request disabled. ‘1’: Interrupt request enabled. Interrupt Enable 5: PLL Unlock / Oscillator Watchdog IE.5 ‘0’: Interrupt request disabled.
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Page 128: Trap Functions
Interrupt and trap functions UM0404 Function Interrupt Flag x CLEAR (x=7...0) FLCLR.x Writing a ‘1’ will clear the corresponding bit x in XIR3SEL register. Writing a ‘0’ has no effect. Interrupt Enable x CLEAR (x=7...0) IECLR.x Writing a ‘1’ will clear the corresponding bit x in XIR3SEL register. Writing a ‘0’... -
Page 129: Software Traps
UM0404 Interrupt and trap functions Table 21. Trap priorities Trap Vector Trap Trap Exception condition Trap flag vector location number priority Class B Hardware Traps: Undefined Opcode UNDOPC BTRAP 00’0028h MAC Interruption MACTRP BTRAP 00’0028h Protected Instruction Fault PRTFLT BTRAP 00’0028h Illegal Word Operand ILLOPA... - Page 130 Interrupt and trap functions UM0404 priority trap is serviced (see Table 5.1: Interrupt system structure on page 96). PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level (level 15), disabling all interrupts.
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Page 131: External Nmi Trap
UM0404 Interrupt and trap functions Function Stack Underflow Flag STKUF The current stack pointer value exceeds the content of register STKUN. Stack Overflow Flag STKOF The current stack pointer value falls below the content of register STKOV. Non Maskable Interrupt Flag A negative transition (falling edge) has been detected on pin NMI. -
Page 132: Stack Underflow Trap
Interrupt and trap functions UM0404 When an implicit decrement of the SP is made through a PUSH or CALL instruction, or upon interrupt or trap entry, the IP value pushed is the address of the following instruction. When the SP is decremented by a subtract instruction, the IP value pushed represents the address of the instruction after the instruction following the subtract instruction. -
Page 133: Illegal Word Operand Access Trap
UM0404 Interrupt and trap functions 5.8.9 Illegal word operand access trap Whenever a word operand read or write access is attempted to an odd byte address, the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine. -
Page 134: Parallel Ports
Parallel ports UM0404 Parallel ports Introduction The ST10F276 has up to 111 parallel I/O lines, organized into: • Eight 8-bit I/O ports (PORT0 made of P0H and P0L, PORT1 made of P1H and P1L, Port4, Port6, Port7, Port8), • One 15-bit I/O port (Port3), •... - Page 135 UM0404 Parallel ports This feature is implemented for ports P2, P3, P4 (partially), P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx. These registers allow the individual bit wise selection of the open drain mode for each port line.
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Page 136: Figure 25. Sfrs, Xbus Registers And Pins Associated With The Parallel Ports
Parallel ports UM0404 Figure 25. SFRs, XBUS registers and pins associated with the parallel ports 136/564 DocID13284 Rev 2... -
Page 137: Input Threshold Control
UM0404 Parallel ports Figure 26. Output drivers in push-pull mode and in open drain mode External Pull-up Push-Pull Output Driver Open Drain Output Driver 6.1.2 Input threshold control The standard inputs of the ST10F276 determine the status of input signals according to TTL levels. -
Page 138: Alternate Port Functions
Parallel ports UM0404 Note: PICON is an ESFR register, while XPICON is an XBUS register. To access XPICON register bit XMISCEN of register XPERCON and bit XPEN of register SYSCON must be set. All options for individual direction and output mode control are available for each pin, independent of the selected input threshold. -
Page 139: Port0
UM0404 Parallel ports On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. -
Page 140: Alternate Functions Of Port0
Parallel ports UM0404 P0H (FF02h / 81h) Reset Value: - - 00h P0H.7P0H.6P0H.5P0H.4P0H.3P0H.2P0H.1P0H.0 Function P0X.y Port data register P0H or P0L bit y DP0L (F100h / 80h) ESFR Reset Value: - - 00h DP0L. DP0L. DP0L. DP0L. DP0L. DP0L. DP0L. DP0L. -
Page 141: Figure 28. Port0 I/O And Alternate Functions
UM0404 Parallel ports With the end of reset, the selected bus configuration will be written to the BUSCON0 register. The configuration of the high byte of PORT0, will be copied into the special register RP0H. This read-only register holds the selection for the number of chip selects and segment addresses. -
Page 142: Port1
Parallel ports UM0404 Figure 29. Block diagram of a PORT0 pin Write DP0H.y / DP0L.y Alternate Direction Direction Latch Read DP0H.y / DP0L.y Alternate Function Enable Alternate Data Output Write P0H.y / P0L.y P0H.y Port Data P0L.y Output Output Port Output Buffer Latch Read P0H.y / P0L.y... -
Page 143: Alternate Functions Of Port1
UM0404 Parallel ports DP1L (F104h / 82h) ESFR Reset Value: - - 00h DP1L. DP1L. DP1L. DP1L. DP1L. DP1L. DP1L. DP1L. DP1H (F106h / 83h) ESFR Reset Value: - - 00h DP1H DP1H DP1H DP1H DP1H DP1H DP1H DP1H Function Port direction register DP1H or DP1L bit y DP1X.y ’0’: Port line P1X.y is an input (high-impedance). -
Page 144: Port1 Analog Inputs Disturb Protection
Parallel ports UM0404 Figure 30. PORT1 I/O and alternate functions Alternate Functions P1H.7 CC27I P1H.6 CC26I P1H.5 CC25I P1H.4 CC24I P1H.3 P1H.2 P1H.1 P1H.0 P1L.7 AN23 P1L.6 AN22 PORT1 P1L.5 AN21 P1L.4 AN20 P1L.3 AN19 P1L.2 AN18 P1L.1 AN17 P1L.0 AN16 General Purpose 8/16-bit... -
Page 145: Figure 31. Block Diagram Of Input Section Of A P1L Pin
UM0404 Parallel ports Function PORT1 Digital Disable register bit y ‘0’: Port line P1.y digital input and output are not disabled: the port pin is defined through the corresponding bits of the standard registers P1L/DP1L. General Purpose Input/Output functionality is available, and also external memory interface functionality. -
Page 146: Port2
Parallel ports UM0404 Figure 32. Block diagram of a PORT1 pin Write DP1H.y / DP1L.y “1” Direction Latch Read DP1H.y / DP1L.y Alternate Function Enable Alternate Data Output Write P1H.y / P1L.y P1H.y Port Data P1L.y Output Output Port Output Buffer Latch Read P1H.y / P1L.y... -
Page 147: Alternate Functions Of Port2
UM0404 Parallel ports Function Port direction register DP2 bit y DP2.y ’0’: Port line P2.y is an input (high-impedance). ’1’: Port line P2.y is an output. ODP2 (F1C2h / E1h) ESFR Reset Value: 0000h ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2... -
Page 148: External Interrupts
Parallel ports UM0404 switched to the line connected to the internal bus. The port output latch will receive the value from the internal bus and the hardware triggered change will be lost. As all other capture inputs, the capture input function of pins P2.7...P2.0 can also be used as external interrupt inputs with a sample rate of eight CPU clock cycles. -
Page 149: Table 22. Port2 Alternate Functions
UM0404 Parallel ports Table 22. Port2 alternate functions Alt. P2 Pin Alternate function b) Alternate function c) Function a) P2.0 CC0IO P2.1 CC1IO P2.2 CC2IO CC3IO P2.3 P2.4 CC4IO P2.5 CC5IO P2.6 CC6IO P2.7 CC7IO P2.8 CC8IO EX0IN Fast External Interrupt 0 Input P2.9 CC9IO EX1IN... -
Page 150: Port3
Parallel ports UM0404 Figure 34. Block diagram of a Port2 pin Write ODP2.y Open Drain Latch Read ODP2.y Write DP2.y Direction Latch Read DP2.y P2.y Output CCyIO Latch Alternate Output EXxIN Data Buffer Output ≥ Write Port P2.y Compare Trigger Read P2.y Clock Input... -
Page 151: Alternate Functions Of Port3
UM0404 Parallel ports DP3 (FFC6h / E3h) Reset Value: 0000h DP3. DP3. DP3. DP3. DP3. DP3. DP3. DP3.7 DP3.6 DP3.5 DP3.4 DP3.3 DP3.2 DP3.1 DP3.0 RW RW RW RW RW RW Function Port direction register DP3 bit y DP3.y ’0’: Port line P3.y is an input (high-impedance). ’1’: Port line P3.y is an output. -
Page 152: Table 23. Port3 Alternative Functions
Parallel ports UM0404 Table 23. Port3 alternative functions Port3 Alternate function P3.0 T0IN CAPCOM1 Timer 0 Count Input P3.1 T6OUT Timer 6 Toggle Output P3.2 CAPIN GPT2 Capture Input T3OUT Timer 3 Toggle Output P3.3 P3.4 T3EUD Timer 3 External Up/Down Input P3.5 T4IN Timer 4 Count Input... -
Page 153: Figure 36. Block Diagram Of A Port3 Pin
UM0404 Parallel ports When using these alternate functions, the user must set the direction of the port line to output (DP3.y = 1) and must set the port output latch (P3.y = 1). Otherwise the pin is in its high-impedance state (when configured as input) or the pin is stuck at '0' (when the port output latch is cleared). -
Page 154: Port4
Parallel ports UM0404 selected automatically. If BHE/WRH is not used in the system, this pin can be used for general purpose I/O by disabling the alternate function (BYTDIS = ‘1’ / WRCFG = ‘0’). Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit DP3.12 = ‘1’... -
Page 155: Alternate Functions Of Port4
UM0404 Parallel ports DP4 (FFCAh / E5h) Reset Value: - - 00h DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0 Function Port direction register DP4 bit y DP4.y ’0’: Port line P4.y is an input (high-impedance). ’1’: Port line P4.y is an output. ODP4 (F1CAh / E5h) Reset Value: - - 00h ODP4. -
Page 156: Table 24. Port4 Alternate Functions
Parallel ports UM0404 Table 24 summarizes the alternate functions of Port4 depending on the number of selected segment address lines (coded via bit-field SALSEL). Table 24. Port4 alternate functions Standard function Alternate function Alternate function Alternate function Port4 SALSEL = 01 SALSEL = 11 SALSEL = 00 SALSEL = 10... -
Page 157: Figure 39. Block Diagram Of Port4 Pins 3
UM0404 Parallel ports Figure 39. Block diagram of Port4 pins 3...0 Write DP4.y “1” Direction Latch Read DP4.y Ext. Memory Function Enable Write P4.y Ext. Memory Data Output P4.y Output Port Output Buffer Latch Read P4.y Clock Input Latch y = 3...0 DocID13284 Rev 2 157/564... -
Page 158: Figure 40. Block Diagram Of P4.4 Pin
Parallel ports UM0404 Figure 40. Block diagram of P4.4 pin Write ODP4.4 Open Drain Latch ‘0’ Read ODP4.4 ‘1’ Write DP4.4 ‘1’ Direction Latch ‘0’ ‘1’ Read DP4.4 Ext. Memory Function Enable Write P4.4 Ext. Memory Data Output Port Output P4.4 Latch Output... -
Page 159: Figure 41. Block Diagram Of P4.5 Pin
UM0404 Parallel ports Figure 41. Block diagram of P4.5 pin Write ODP4.5 Open Drain Latch ‘0’ Read ODP4.5 Write DP4.5 ‘1’ Direction Latch ‘0’ Read DP4.5 Ext. Memory Function Enable Write P4.5 Ext. Memory Data Output P4.5 Port Output Latch Output Buffer Read P4.5... -
Page 160: Figure 42. Block Diagram Of P4.6 Pin
Parallel ports UM0404 Figure 42. Block diagram of P4.6 pin Write ODP4.6 Open Drain Latch ‘0’ Read ODP4.6 Write DP4.6 ‘1’ Direction Latch ‘1’ Read DP4.6 Ext. Memory Function Enable Write P4.6 Ext. Memory Data Output Port Output P4.6 Latch Output Read P4.6 Buffer... -
Page 161: Port5
UM0404 Parallel ports Figure 43. Block diagram of P4.7 pin Write ODP4.7 Open Drain Latch ‘0’ Read ODP4.7 ‘1’ Write DP4.7 ‘1’ Direction Latch ‘1’ ‘1’ Read DP4.7 Ext. Memory Function Enable Write P4.7 Ext. Memory Data Output Port Output Latch P4.7 Read P4.7... -
Page 162: Alternate Functions Of Port5
Parallel ports UM0404 P5 (FFA2h / D1h) Reset Value: xxxxh P5.15P5.14P5.13P5.12 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 Function P5.y Port data register P5 bit y (Read only) 6.7.1 Alternate functions of Port5 Each line of Port5 is also connected to the input multiplexer of the analog/digital converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0) that can be converted by the ADC. -
Page 163: Port5 Analog Inputs Disturb Protection
UM0404 Parallel ports Figure 44. Port5 I/O and alternate functions Alternate Functions P5.15 AN15 T2EUD P5.14 AN14 T4EUD P5.13 AN13 T5IN P5.12 AN12 T6IN P5.11 AN11 T5EUD P5.10 AN10 T6EUD P5.9 P5.8 P5.7 P5.6 Port5 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 General Purpose A/D Converter Input... -
Page 164: Port6
Parallel ports UM0404 Function Port5 Digital Disable register bit y ’0’: Port line P5.y digital input is enabled (Schmitt trigger enabled). P5DIDIS.y ’1’: Port line P5.y digital input is disabled (Schmitt trigger disabled, necessary for input leakage current reduction). Port6 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. -
Page 165: Alternate Functions Of Port6
UM0404 Parallel ports Function Port Open-Drain control register ODP6 bit y ODP6.y ’0’: Port line P6.y output driver in push-pull mode. ’1’: Port line P6.y output driver in open drain mode. XSSCPORT (E880h) XBUS Reset Value: 0000h XDP6 XDP6 XDP6 P6.7 P6.6 P6.5... -
Page 166: Table 26. Port6 Alternate Functions
Parallel ports UM0404 Table 26. Port6 alternate functions Alternate function Alternate function Alternate function Alternate function Port6 pin CSSEL = 10 CSSEL = 01 CSSEL = 00 CSSEL = 11 P6.0 General purpose I/O Chip select CS0 Chip select CS0 Chip select CS0 P6.1 General purpose I/O... -
Page 167: Figure 47. Block Diagram Of Port6 Pins 4
UM0404 Parallel ports Note: The open drain output option can only be selected via software earliest during the initialization routine; at least signal CS0 will be in push-pull output driver mode directly after reset (see Figure 47). The bus arbitration signals HOLD, HLDA and BREQ are selected with bit HLDEN in register PSW. -
Page 168: Figure 48. Block Diagram Of P6.5 Pin
Parallel ports UM0404 Figure 48. Block diagram of P6.5 pin Write ODP6.5 Open Drain Latch Read ODP6.5 Write DP6.5 Direction Latch Read DP6.5 Write P6.5 Port Output Latch P6.5 Read P6.5 Output Buffer & SCLK1 Clock Data Output Input Latch Write XODP6.5 Open Drain Latch... -
Page 169: Port7
UM0404 Parallel ports Port7 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push-pull or open-drain mode via the open-drain control register ODP7. P7 (FFD0h / E8h) Reset Value: - - 00h P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0... -
Page 170: Table 27. Port7 Alternate Functions
Parallel ports UM0404 The lower four lines of Port7 (P7.3...P7.0) supports outputs of the PWM module (POUT3...POUT0). At these pins the value of the respective port output latch is XORed with the value of the PWM output rather than ANDed, as the other pins do. This allows to use the alternate output value either as it is (port latch holds a ‘0’) or invert its level at the pin (port latch holds a ‘1’). -
Page 171: Figure 50. Block Diagram Of Port7 Pins 3
UM0404 Parallel ports Figure 50. Block diagram of Port7 pins 3...0 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y Alternate Data Output Write P7.y Port Data P7.y / POUTy Output Port Output Output Latch Buffer Read P7.y Clock Input... -
Page 172: Port8
Parallel ports UM0404 Figure 51. Block diagram of Port7 pins 7...4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y Output P7.y Latch CCzIO Alternate Output Data Buffer Output Write Port P7.y ≥ Compare Trigger Read P7.y Clock y = (7...4) Input... - Page 173 UM0404 Parallel ports XPWMPORT and XS1PORT registers (mapped on XBUS) which again allows the user to program pin P8.0-P8.3 and P8.6-P8.7 respectively, according to the XPWM an XASC configurations. P8 (FFD4h / EAh) Reset Value: - - 00h P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 Function P8.y Port data register P8 bit y...
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Page 174: Alternate Functions Of Port8
Parallel ports UM0404 Function Port direction register bit y (y = 0, 1, 2, 3 only) XDP8.y ‘0’: Port line P8.y is an input (high-impedance). ‘1’: Port line P8.y is an output. XP8.y Port data register bit y (y = 0, 1, 2, 3 only) Port Open Drain control register bit y (y = 0, 1, 2, 3 only) XODP8.y ‘0’: Port line P8.y output driver in push/pull mode. -
Page 175: Table 28. Port8 Alternate Functions
UM0404 Parallel ports Table 28. Port8 alternate functions Port8 Alternate function a) Alternate function b) XPOUT0XPWM channel 0 output P8.0 CC16IO Capture input / compare output ch. 16 XPOUT1XPWM channel 1 output P8.1 CC17IO Capture input / compare output ch. 17 XPOUT2XPWM channel 2 output P8.2 CC18IO Capture input / compare output ch. -
Page 176: Figure 53. Block Diagram Of Port8 Pins 3
Parallel ports UM0404 Figure 53. Block diagram of Port8 pins 3...0 Write ODP8.y Open Drain Latch Read ODP8.y Write DP8.y Direction Latch Read DP8.y Port Output Latch CCzIO P8.y Data Output Output Buffer ≥ 1 Write P8.y XPOUTy Data Output Compare Trigger EXOR Read P8.y... -
Page 177: Figure 54. Block Diagram Of P8.4 And P8.5 Pins
UM0404 Parallel ports Figure 54. Block diagram of P8.4 and P8.5 pins Write ODP8.y Open Drain Latch Read ODP8.y Write DP8.y Direction Latch Read DP8.y Port Output P8.y Latch CCzIO Data Output Output Buffer ≥ 1 Write P8.y Compare Trigger Read P8.y Clock Input... -
Page 178: Figure 55. Block Diagram Of P8.6 Pin
Parallel ports UM0404 Figure 55. Block diagram of P8.6 pin Write ODP8.6 Open Drain Latch Read ODP8.6 Write DP8.6 Direction Latch Read DP8.6 Port Output Latch CC22IO P8.6 Data Output Output Buffer ≥ 1 Write P8.6 RxD1 Data Output Compare Trigger &... -
Page 179: Dedicated Pins
UM0404 Dedicated pins Dedicated pins Most of the input/output or control signals of the ST10F276 are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the oscillator, special control signals and the power supply. Table 29 summarizes the dedicated pins of the ST10F276. -
Page 180: Figure 56. Rpd External Rc Circuit
Dedicated pins UM0404 Table 29. Summary of dedicated pins (continued) Pin(s) Function Reset Input: puts the ST10F276 into the reset default configuration either at Power-On or RSTIN external events like a hardware failure or manual reset. The input circuitry of the RSTIN pin implements an analog filter in order to minimize the noise sensitivity of the reset input. -
Page 181: The External Bus Interface
UM0404 The external bus interface The external bus interface The on-chip peripherals and the on-chip RAM and Flash Memory only cover a small fraction of the ST10F276 address space. The external bus interface gives access to external peripherals and additional volatile and non-volatile memory. It provides a number of configurations and can be tailored to fit perfectly into a given application system. -
Page 182: Figure 57. Sfrs And Port Pins Associated With The External Bus Interface
The external bus interface UM0404 Figure 57. SFRs and port pins associated with the external bus interface Ports & Direction Control Alternate Functions Control Registers P0L/P0H SYSCON P1L/P1H Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y RP0H - - - Y Y Y Y Y Y Y Y - Y -... -
Page 183: External Bus Modes
UM0404 The external bus interface External bus modes When the external bus interface is enabled (bit BUSACTx = ‘1’ of BUSCONx register) and configured (bit-field BTYP), the ST10F276 uses a subset of its port lines together with some control lines to build the external bus. BTYP encoding External data bus width External address bus mode... -
Page 184: De-Multiplexed Bus Modes
The external bus interface UM0404 Read cycles: Input data is latched and the command signal is now de-activated. This causes the accessed device to remove its data from the bus which is then tri-stated again. Write cycles: The command signal is now deactivated. The data remain valid on the bus until the next external bus cycle is started. -
Page 185: Switching Between The Bus Modes
UM0404 The external bus interface Figure 59. De-multiplexed bus cycle Bus Cycle Segment (P1) Address Segment (P4) BUS (P0) Data/Instr. BUS (P0) Data 8.2.3 Switching between the bus modes The EBC allows dynamic switching between different bus modes: this means that subsequent external bus cycles may be executed in different ways. -
Page 186: External Data Bus Width
The external bus interface UM0404 uses the default configuration in BUSCON0. After initializing the active registers, they are selected and evaluated automatically by interpreting the physical address. No additional switching or selecting is necessary during run time, except when more than the four address windows plus the default is to be used. -
Page 187: Disable / Enable Control For Pin Bhe (Bytdis)
UM0404 The external bus interface Figure 60. Switching from de-multiplexed to multiplexed bus mode De-multiplexed Multiplexed Bus Cycle Idle State Bus Cycle Address (P1) Address Address Segment (P4) BUS (P0) Data/Instr. Data/Instr. Address BUS (P0) Address Data Data Transfer Rate Free I/O Bus Mode (Speed factor for byte/word/Dword... -
Page 188: Cs Signal Generation
The external bus interface UM0404 accessible address space. The number of segment address lines is selected during reset and coded in bit-field SALSEL in register RP0H (see table below). SALSEL Segment address lines Directly accessible address space 256 Kbytes (Default without pull-downs on Two: A17...A16 Eight: A23...A16 16 Mbytes (Maximum) -
Page 189: Segment Address Versus Chip Select
UM0404 The external bus interface CSWENx CSRENx Chip select mode Write Chip Select Read/Write Chip Select Address chip select signals remain active until an access to another address window. An address chip select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area. -
Page 190: Programmable Bus Characteristics
The external bus interface UM0404 Programmable bus characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and/or peripherals. The following parameters of an external bus cycle are programmable: •... -
Page 191: Programmable Memory Cycle Time
UM0404 The external bus interface cycle refers to the same CLKOUT edges as usual (the data transfer is delayed by one CPU clock cycle). This allows more time for the address to be latched. Note: ALECTL0 is ‘1’ after reset to select the slowest possible bus cycle, the other ALECTLx are ‘0’... -
Page 192: Programmable Memory Tri-State Time
The external bus interface UM0404 Figure 63. Memory cycle time Bus Cycle Segment Address BUS (P0) Address Data/Instr. BUS (P0) Address Data MCTC Wait States (1...15) 8.3.3 Programmable memory tri-state time The ST10F276 allows the user to adjust the time between two subsequent external accesses to address slow external devices. -
Page 193: Read / Write Signal Delay
UM0404 The external bus interface Figure 64. Memory tri-state time Bus Cycle Segment Address BUS (P0) Address Data/instr. MTTC Wait State 8.3.4 Read / write signal delay The ST10F276 allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals. -
Page 194: Ready Polarity
The external bus interface UM0404 Figure 65. Read / write delay Bus Cycle Segment Address BUS (P0) Data/Instr. Data BUS (P0) Address Read / Write Delay 1) The data drivers from the previous bus cycle should be disabled when the RD signal becomes active. 8.3.5 READY polarity The active level of the ready pin can be set to READY or READY by the RDYPOL bit 13 in... -
Page 195: Figure 66. Ready/Ready Controlled Bus Cycles
UM0404 The external bus interface The synchronous READY/READY (SREADY / SREADY) provides the fastest bus cycles, but requires setup and hold times to be met. The CLKOUT signal should be enabled and may be used by the peripheral logic to control the READY/READY timing in this case. The asynchronous READY/READY (AREADY / AREADY) is less restrictive, but requires additional wait-states caused by the internal synchronization. -
Page 196: Programmable Chip Select Timing Control
The external bus interface UM0404 drive it low again. If, however, the peripheral deactivates READY/READY after the first sample point of the ST10F276, the controller samples an active READY/READY and terminates the current bus cycle, which, of course, is too early. By inserting predefined wait-states the first READY/READY sample point can be shifted to a time, where the peripheral has safely controlled the READY/READY line (after two wait-states in the Figure... - Page 197 UM0404 The external bus interface The properties of a bus cycle like chip select mode, usage of READY, length of ALE, external bus mode, read/write delay and wait-states are controlled by BUSCON4...BUSCON0 registers. Four of these registers (BUSCON4...BUSCON1) have an associated address select register (ADDRSEL4...ADDRSEL1) which allows to specify up to four address areas and the individual bus characteristics within these areas.
- Page 198 The external bus interface UM0404 Function Chip Select Configuration Control CSCFG ‘0’: Latched Chip Select lines, CSx changes 1 TCL after rising edge of ALE. ‘1’: Unlatched Chip Select lines, CSx changes with rising edge of ALE. Write Configuration Control (Inverted copy of WRC bit of RP0H) WRCFG ‘0’: Pins WR and BHE retain their normal function.
- Page 199 UM0404 The external bus interface BUSCON2 (FF16h / 8Bh) Reset Value: 0000h CSWEN2 CSREN2 RDYPOL2 RDYEN2 BUSACT2 ALECTL2 BTYP MTTC2 RWDC2 MCTC BUSCON3 (FF18h / 8Ch) Reset Value: 0000h CSWEN3 CSREN3 RDYPOL3 RDYEN3 BUSACT3 ALECTL3 BTYP MTTC3 RWDC3 MCTC BUSCON4 (FF1Ah / 8Dh) Reset Value: 0000h CSWEN4 CSREN4 RDYPOL4 RDYEN4 BUSACT4 ALECTL4...
- Page 200 The external bus interface UM0404 Function Read Chip Select Enable CSRENx ‘0’: The CS signal is independent of the read command (RD). ‘1’: The CS signal is generated for the duration of the read command. Write Chip Select Enable CSWENx ‘0’: The CS signal is independent of the write command (WR, WRL, WRH).
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Page 201: Definition Of Address Areas
UM0404 The external bus interface 8.4.1 Definition of address areas The four register pairs BUSCON4/ADDRSEL4...BUSCON1/ADDRSEL1 allow to define four separate address areas within the address space of the ST10F276. Within each of these address areas external accesses can be controlled by one of the four different bus modes, independent of each other and of the bus mode specified in register BUSCON0. -
Page 202: Figure 68. Address Window Arbitration
The external bus interface UM0404 Figure 68. Address window arbitration XBCONx Active Window BUSCON2 BUSCON4 Inactive BUSCON1 BUSCON3 Window BUSCON0 Note: Only the indicated overlaps are defined. All other overlaps lead to erroneous bus cycles. ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1. The hard-wired (or programmable) XADRSx registers are defined non-overlapping. -
Page 203: Precautions And Hints
UM0404 The external bus interface 8.4.3 Precautions and hints • The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set. • PORT1 will output the intra-segment address as long as at least one of the BUSCON registers selects a de-multiplexed external bus, even for multiplexed bus cycles. -
Page 204: External Bus Arbitration
The external bus interface UM0404 External bus arbitration In high performance systems it may be efficient to share external resources like memory banks or peripheral devices among more than one controller. The ST10F276 supports this approach with the possibility to arbitrate the access to its external bus, and to the external devices. -
Page 205: Entering The Hold State
UM0404 The external bus interface DP6.7 = ‘0’) while the other one must be operated in its slave mode (selected with DP6.7 = ‘1’). In slave mode the ST10F276 inverts the direction of its HLDA pin and uses it as an input, while the master’s HLDA pin remains an output. -
Page 206: Exiting The Hold State
The external bus interface UM0404 Figure 70. External bus arbitration, releasing the bus HOLD HLDA BREQ Other Signals Note: The ST10F276 will complete the currently running bus cycle before granting bus access as indicated by the broken lines. This may delay hold acknowledge compared to this figure. The figure above shows the first possibility for BREQ to get active. -
Page 207: The Xbus Interface
UM0404 The external bus interface Figure 71. External bus arbitration, (regaining the bus) HOLD HLDA BREQ Other Signals Note: The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain- sequence. Even if BREQ is activated earlier the regain-sequence is initiated by HOLD going high. -
Page 208: Table 32. Definition Of Xbus Address Areas
The external bus interface UM0404 Function Range Size Selection RGSZ Defines the size of the address area controlled by the respective XBCONx/XADRSx register pair. See Table Range Start Address RGSAD Defines the upper bit of the start address (A19...) of the respective address area. Table The register functionality is the same as the one of ADDRSELx registers used for external address range selection. - Page 209 UM0404 The external bus interface port pins and interrupts are not occupied by the peripheral, the peripheral is then not visible or available. Refer to Chapter 26: Register set. DocID13284 Rev 2 209/564...
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Page 210: Figure 72. Memory Mapping (User Mode: Flash Read Operations / Xadrs = 800Bh)
The external bus interface UM0404 Figure 72. Memory mapping (User mode: Flash read operations / XADRS = 800Bh) Code Data Data Code Page Page RAM / SFR (4Kbyte) Segment Segment FF FFFF 1023 11 FFFF Ext. Memory 01 0000 00 FFFF 00 FFFF 11 0000 00 FE00... -
Page 211: Figure 73. Memory Mapping (User Mode: Flash Read Operations / Xadrs = C00Ah)
UM0404 The external bus interface Figure 73. Memory mapping (User mode: Flash read operations / XADRS = C00Ah) Code Data Data Code Page Page RAM / SFR (4Kbyte) Segment Segment FF FFFF 1023 11 FFFF Ext. Memory 01 0000 00 FFFF 00 FFFF 11 0000 00 FE00... - Page 212 The external bus interface UM0404 XPERCON (F024h / 12h) ESFR Reset Value: - 005h XMISC XI2C XSSC XASC XPWM XFLAS XRTC XRAM2 XRAM1 CAN2 CAN1 Function CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5 and P4.6 pins can be used as general purpose IOs, but address range 00’EC00h- CAN1EN 00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,...
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Page 213: Ea Functionality
UM0404 The external bus interface Function XSSC Enable Bit ‘0’: Accesses to the on-chip XSSC are disabled, external access performed. Address XSSCEN range 00’E800h-00’E8FFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also. ‘1’: The on-chip XSSC is enabled and can be accessed. -
Page 214: Figure 74. Ea / Vstby External Circuit
The external bus interface UM0404 Figure 74. EA / V external circuit STBY 4 - 5.5 Volt EA / V STBY STBY EA function ST10F276 Figure 74 the diagram of a possible external circuit is reported. Attention should be paid in implementing the resistance for current limitation of bipolar: the same resistance should not disturb the Stand-by mode when some current (in the order of hundreds of µA) is provided to the device by the V... -
Page 215: The General Purpose Timer Units
UM0404 The general purpose timer units The general purpose timer units The general purpose timer units GPT1 and GPT2 are flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. -
Page 216: Figure 75. Sfrs And Port Pins Associated With Timer Block Gpt1
The general purpose timer units UM0404 Figure 75. SFRs and port pins associated with timer block GPT1 Ports & Direction Control Alternate Functions Data Registers ODP3 E - - - Y Y Y Y Y - - - T3 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - - - Y Y Y Y Y - - - T4 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -... -
Page 217: Gpt1 Core Timer T3
UM0404 The general purpose timer units Figure 76. GPT1 block diagram T2EUD P5.15 Interrupt GPT1 Timer T2 Request CPU Clock n=3...10 T2IN Reload Mode P3.7 Capture CPU Clock T3OUT n=3...10 T3OTL GPT1 Timer T3 T3IN Mode P3.6 P3.3 T3EUD P3.4 Capture Reload Interrupt... -
Page 218: Table 33. Gpt1 Core Timer T3 Count Direction Control
The general purpose timer units UM0404 Function T3UDE Timer 3 External Up/Down Enable Alternate Output Function Enable T3OE T3OE = ‘0’:Alternate Output Function Disabled - T3OE = ‘1’: Alternate Output Function Enabled Timer 3 Output Toggle Latch - Toggles on each overflow / underflow of T3. Can be set or T3OTL reset by software. -
Page 219: Figure 77. Core Timer T3 In Timer Mode
UM0404 The general purpose timer units Note: The direction control works the same for core timer T3 and for auxiliary timers T2 and T4. Therefore the pins and bits are named Tx... Timer 3 output toggle latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON. -
Page 220: Table 34. Gpt1 Timer Resolutions
The general purpose timer units UM0404 The timer resolutions which result from the selected pre-scaler option are listed in the . This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 Table 34 and T4 in timer and gated timer mode. -
Page 221: Table 35. Gpt1 Core Timer T3 (Counter Mode) Input Edge Selection
UM0404 The general purpose timer units Figure 78. Core timer T3 in gated timer mode Clock Interrupt Core Timer T3 T3IR T3IN Request P3.6 Up/Down T3OUT T3OTL P3.3 T3UD T3OE T3EUD P3.4 T3UDE Figure 79. Core timer T3 in counter mode Edge Select T3IN... -
Page 222: Table 36. Gpt1 Core Timer T3 (Incremental Interface Mode) Input Edge Selection
The general purpose timer units UM0404 To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized, its level should be held high or low for at least 8 CPU clock cycles before it changes. -
Page 223: Figure 81. Connection Of The Encoder To The St10F276
UM0404 The general purpose timer units Figure 81. Connection of the encoder to the ST10F276 T3input T3input ST10F276x Interrupt Signal Conditioning For incremental interface operation the following conditions must be met • Bit-field T3M must be ‘110b’ • Both pins T3IN and T3EUD must be configured as input, at the respective direction control bit with ‘0’. -
Page 224: Gpt1 Auxiliary Timers T2 And T4
The general purpose timer units UM0404 Figure 82. Evaluation of the incremental encoder signals forward jitter backward jitter forward T3IN T3EUD Contents of T3 down Note: This example shows the timer behavior assuming that T3 counts upon any transition on any input, T3I=’011b’... - Page 225 UM0404 The general purpose timer units timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The auxiliary timers have no output toggle latch and no alternate output function. The individual configuration for timers T2 and T4 is determined by their bit-addressable control registers T2CON and T4CON, which are both organized identically.
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Page 226: Table 37. Gpt1 Auxiliary Timer (Counter Mode) Input Edge Selection
The general purpose timer units UM0404 tables apply accordingly with one exception: There is no output toggle latch and no alternate output pin for T2 and T4. Timers T2 and T4 in counter mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit-field TxM in the respective register TxCON to ‘001b’. - Page 227 UM0404 The general purpose timer units Table 37. GPT1 auxiliary timer (counter mode) input edge selection T2I / T4I Triggering edge for counter increment / decrement 1 1 0 Negative transition (falling edge) of output toggle latch T3OTL 1 1 1 Any transition (rising or falling edge) of output toggle latch T3OTL Timer concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode...
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Page 228: Figure 85. Concatenation Of Core Timer T3 And An Auxiliary Timer
The general purpose timer units UM0404 Figure 85. Concatenation of core timer T3 and an auxiliary timer Interrupt Core Timer T3 T3IR Clock Request T3OUT T3OTL Up/Down P3.3 T3OE Edge Select Interrupt Auxiliary Timer Tx TxIR Request x = 2,4 Note: 1. - Page 229 UM0404 The general purpose timer units The reload mode triggered by T3OTL can be used in a number of different configurations. Depending on the selected active transition the following functions can be performed: • If both a positive and a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows.
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Page 230: Figure 87. Gpt1 Timer Reload Configuration For Pwm Generation
The general purpose timer units UM0404 Figure 87. GPT1 timer reload configuration for PWM generation Reload Register T2 Interrupt T2IR Request Input T3OUT T3OTL Core Timer T3 Clock P3.3 Up/Down T3OE Interrupt T3IR Request Interrupt T4IR Request Reload Register T4 Note: Lines only affected by over/underflows of T3, but NOT by software modifications of T3OTL. -
Page 231: Interrupt Control For Gpt1 Timers
UM0404 The general purpose timer units Figure 88. GPT1 auxiliary timer in capture mode Edge Select Capture Register Tx TxIN Interrupt P3.7 TxIR Request P3.5 Input Interrupt Core Timer T3 T3IR Clock Request T3OUT Up/Down T3OTL P3.3 x = 2, 4 T3OE Upon a trigger (selected transition) at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request... -
Page 232: Timer Block Gpt2
The general purpose timer units UM0404 Timer block GPT2 From a programmer's point of view, the GPT2 block is represented by a set of SFRs. The I/O of port and direction registers which are used for alternate functions by the GPT2 block are noted ‘Y’... -
Page 233: Figure 89. Sfrs And Port Pins Associated With Timer Block Gpt2
UM0404 The general purpose timer units Figure 89. SFRs and port pins associated with timer block GPT2 Ports & Direction Control Alternate Functions Data Registers ODP3 E - - - - - - - - Y Y - Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - - - - - - - - Y Y - CAPREL Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - Y Y Y Y - - - - - - - - - -... -
Page 234: Gpt2 Core Timer T6
The general purpose timer units UM0404 Figure 90. GPT2 block diagram T5EUD P5.11 CPU Clock n=2...9 Interrupt GPT2 Timer T5 T5IN Request P5.13 Mode Clear Capture Interrupt CAPIN Request P3.2 GPT2 CAPREL Reload Interrupt Request T6IN P5.12 GPT2 Timer T6 T6OUT T6OTL CPU Clock... -
Page 235: Table 38. Gpt2 Core Timer T6 Count Direction Control
UM0404 The general purpose timer units Function T6UDE Timer 6 External Up/Down Enable Alternate Output Function Enable T6OE T6OE = ‘0’: Alternate Output Function Disabled T6OE = ‘1’: Alternate Output Function Enabled Timer 6 Output Toggle Latch T6OTL Toggles on each overflow / underflow of T6. Can be set or reset by software. Timer 6 Reload Mode Enable T6SR T6SR = ‘0’: Reload from register CAPREL Disabled... -
Page 236: Figure 91. Block Diagram Of Core Timer T6 In Timer Mode
The general purpose timer units UM0404 Timer 6 output toggle latch An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON. T6OTL can also be set or reset by software. Bit T6OE (Alternate Output Function Enable) in register T6CON enables the state of T6OTL to be an alternate function of the external output pin T6OUT/P3.1. -
Page 237: Table 39. Gpt2 Timer Resolution
UM0404 The general purpose timer units Table 39. GPT2 timer resolution Timer input selection T5I / T6I 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler factor Resolution in CPU clock cycles Refer to the device datasheet for a table of timer input frequencies, resolution and periods for the range of pre-scaler options. -
Page 238: Table 40. Gpt2 Core Timer T6 (Counter Mode) Input Edge Selection
The general purpose timer units UM0404 Figure 93. Block diagram of core timer T6 in counter mode Edge Select T6IN Interrupt P5.12 Core Timer T6 T6IR Request Up/Down T6OUT T6OTL P3.1 T6UD T6OE T6EUD P5.10 T6UDE Table 40. GPT2 core timer T6 (counter mode) input edge selection Triggering edge for counter increment / decrement 0 0 0 None. - Page 239 UM0404 The general purpose timer units Function Timer 5 Input Selection Depends on the Operating Mode, see respective sections. Timer 5 Mode Control (Basic Operating Mode) 0 0: Timer Mode 0 1: Counter Mode 1 0: Gated Timer with Gate active low 1 1: Gated Timer with Gate active high Timer 5 Run bit T5R = ‘0’:...
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Page 240: Table 41. Gpt2 Auxiliary Timer (Counter Mode) Input Edge Selection
The general purpose timer units UM0404 (see Figure 94). Bit-field T5I in control register T5CON selects the triggering transition (see Table 41 Note: Only state transitions of T6OTL which are caused by the overflows/underflows of T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of T5. - Page 241 UM0404 The general purpose timer units T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit timer / counter. • 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL is used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6.
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Page 242: Figure 95. Concatenation Of Core Timer T6 And Auxiliary Timer T5
The general purpose timer units UM0404 Figure 95. Concatenation of core timer T6 and auxiliary timer T5 Interrupt Core Timer T6 T6IR Clock Request T6OUT T6OTL Up/Down P3.1 T6OE Edge Select Interrupt Auxiliary Timer T5 T5IR Request Note: Line only affected by over/underflows of T6, but NOT by software modifications of T6OTL. Figure 96. -
Page 243: Figure 97. Gpt2 Register Caprel In Reload Mode
UM0404 The general purpose timer units Figure 97. GPT2 register CAPREL in reload mode CAPREL Register T6OUT T6OTL P3.1 T6SR T6OE Input Interrupt Core Timer T6 T6IR Clock Request To CAPCOM Up/Down Timers GPT2 capture / reload register CAPREL in capture-and-reload mode Since the reload function and the capture function of register CAPREL can be enabled individually by bit T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. -
Page 244: Interrupt Control For Gpt2 Timers And Caprel
The general purpose timer units UM0404 Figure 98. GPT2 register CAPREL in capture-and-reload mode Up/Down Input Interrupt Auxiliary Timer T5 T5IR Clock Request Edge Select T5CLR CAPIN P3.2 T5SC Interrupt CRIR Request CAPREL Register T6OUT T6OTL P3.1 T6SR T6OE Interrupt Input Core Timer T6 T6IR... - Page 245 UM0404 The general purpose timer units CRIC (FF6Ah / B5h) Reset Value: - - 00h CRIR CRIE ILVL GLVL Note: Refer to Chapter 5.1.3 for explanation of the control fields. DocID13284 Rev 2 245/564...
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Page 246: Asynchronous / Synchronous Serial Interface
Asynchronous / synchronous serial interface UM0404 Asynchronous / synchronous serial interface The Asynchronous/Synchronous Serial Interface ASC0 provides serial communication between the ST10F276 and other microcontrollers, microprocessors or external peripherals. In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F276. - Page 247 UM0404 Asynchronous / synchronous serial interface The operating mode of the serial channel ASC0 is controlled by its bit-addressable control register S0CON. This register contains control bit for mode and error check selection, and status flags for error identification. S0CON (FFB0h / D8h) Reset Value: 0000h S0LB S0BRS S0ODD S0OE S0FE...
- Page 248 Asynchronous / synchronous serial interface UM0404 Function Loopback Mode Enable bit S0LB Standard transmit/receive mode Loopback mode enabled Baud rate Generator Run bit Baud rate generator disabled (ASC0 inactive) Baud rate generator enabled A transmission is started by writing to the Transmit Buffer register S0TBUF (via an instruction or a PEC data transfer).
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Page 249: Asynchronous Operation
UM0404 Asynchronous / synchronous serial interface S0RBUF (FEB2h / 59h) Reset Value: 0xxxh Received Data 10.1 Asynchronous operation Asynchronous mode supports full-duplex communication, where both transmitter and receiver use the same data frame format and the same Baud rate. Data is transmitted on pin TXD0/P3.10 and received on pin RXD0/P3.11. -
Page 250: Figure 101. Asynchronous 8-Bit Data Frames
Asynchronous / synchronous serial interface UM0404 modulo-2-sum of the 7 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF in 8-bit data mode). The parity error flag S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received. -
Page 251: Synchronous Operation
UM0404 Asynchronous / synchronous serial interface The transmit interrupt request flag S0TIR will be set before the last bit of a frame is transmitted, that means before the first or the second stop bit is shifted out of the transmit shift register. -
Page 252: Figure 103. Synchronous Mode Of Serial Channel Asc0
Asynchronous / synchronous serial interface UM0404 Figure 103. Synchronous mode of serial channel ASC0 Reload Register Baud Rate Timer Clock S0M = 000b S0OE Receive Interrupt S0RIR Clock Request S0REN S0OEN Transmit S0TIR Interrupt Serial Port Control S0LB Output Request TDX0 Error Shift Clock... -
Page 253: Hardware Error Detection
UM0404 Asynchronous / synchronous serial interface Pin TXD0/P3.10 must be configured for alternate data output, P3.10 = ‘1’ and DP3.10 = ‘1’, in order to provide the shift clock. Pin RXD0/P3.11 must be configured as alternate data input (DP3.11 = ‘0’). Synchronous reception is stopped by clearing bit S0REN. -
Page 254: Asc0 Interrupt Control
Asynchronous / synchronous serial interface UM0404 An auto-reload of the timer with the content of the reload register is performed each time S0BG is written to. However, if S0R = ‘0’ at the time the write operation to S0BG is performed, the timer will not be reloaded until the first instruction cycle after S0R = ‘1’. - Page 255 UM0404 Asynchronous / synchronous serial interface The cause of an error interrupt request (framing, parity, overrun error) can be identified by the error status flags in control register S0CON. Note: In contrary to the error interrupt request flag S0EIR, the error status flags S0FE/S0PE/S0OE are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software.
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Page 256: Figure 104. Asc0 Interrupt Generation
Asynchronous / synchronous serial interface UM0404 Using the transmit buffer interrupt (S0TBIR) to reload transmit data gives the time to transmit a complete frame for the service routine, as S0TBUF may be reloaded while the previous data is still being transmitted. As shown in the Figure 104, S0TBIR is an early trigger for the reload routine, while S0TIR... -
Page 257: Xbus Asynchronous / Synchronous Serial Interface
UM0404 XBUS asynchronous / synchronous serial interface XBUS asynchronous / synchronous serial interface A second Asynchronous/Synchronous Serial Interface (XASC) is implemented on ST10F276. It is mapped on XBUS interface (Address range 00’E900h-00’E9FFh) and provides serial communication between the ST10F276 and other microcontrollers, microprocessors or external peripherals. -
Page 258: Figure 105. Xbus Registers And Port Pins Associated With Xasc
XBUS asynchronous / synchronous serial interface UM0404 Figure 105. XBUS registers and port pins associated with XASC Ports & Direction Control Alternate Functions Data Registers XS1PORT XS1BG XS1TBUF - - - Y Y Y Y Y Y Y Y Y XS1RBUF - - - Y Y Y Y Y Y Y Y Y Control Registers... - Page 259 UM0404 XBUS asynchronous / synchronous serial interface Function XASC Mode Control 0 0 0: 8-bit data synchronous operation 0 0 1: 8-bit data asynchronous operation 0 1 0: Reserved. Do not use this combination 0 1 1: 7-bit data + parity asynchronous operation 1 0 0: 9-bit data asynchronous operation...
- Page 260 XBUS asynchronous / synchronous serial interface UM0404 XS1CONSET (E902h) XBUS Reset Value: 0000h SET.1 SET.1 SET.1 SET.1 SET.1 SET.9 SET.8 SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0 Function Writing a ‘1’ will set the corresponding bit in XS1CON register. SET.y Writing a ‘0’...
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Page 261: Asynchronous Operation
UM0404 XBUS asynchronous / synchronous serial interface Note: Serial data transmission or reception is only possible when the Baud rate Generator Run bit S1R is set to ‘1’. Otherwise the serial interface is idle. Do not program the mode control field S1M in register XS1CON to one of the reserved combinations to avoid unpredictable behavior of the serial interface. -
Page 262: Figure 106. Asynchronous Mode Of Serial Channel Xasc
XBUS asynchronous / synchronous serial interface UM0404 Figure 106. Asynchronous mode of serial channel XASC Reload Register Baud Rate Timer Clock S1M S1STP S1FE S1PE S1OE Receive Interrupt Clock Request S1REN S1FEN Transmit Interrupt S1PEN Serial Port Control Request S1OEN RXD1 Input P8.6 S1LB... - Page 263 UM0404 XBUS asynchronous / synchronous serial interface 9-bit data frames either consist of 9 data bits D8...D0 (S1M = ‘100b’), of 8 data bits D7...D0 plus an automatically generated parity bit (S1M = ‘111b’) or of 8 data bit D7...D0 plus wake- up bit (S1M = ‘101b’).
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Page 264: Synchronous Operation
XBUS asynchronous / synchronous serial interface UM0404 Figure 108. Asynchronous 9-bit data frames (1st) Start Stop Stop (LSB) • Data bit D8 • Parity • Wake-up bit When the last stop bit has been received, the content of the receive shift register is transferred to the receive data buffer register XS1RBUF. -
Page 265: Figure 109. Synchronous Mode Of Serial Channel Xasc
UM0404 XBUS asynchronous / synchronous serial interface Figure 109. Synchronous mode of serial channel XASC Reload Register Baud Rate Timer Clock S1M = 000b S1OE Receive Interrupt Clock Request S1REN S1OEN Transmit Interrupt Serial Port Control S1LB Output Request TDX0 Error Shift Clock P8.7... -
Page 266: Hardware Error Detection
XBUS asynchronous / synchronous serial interface UM0404 Pin TXD1/P8.7 must be configured for alternate data output, P8.7 = ‘1’ and DP8.7 = ‘1’, in order to provide the shift clock. Pin RXD1/P8.6 must be configured as alternate data input (DP8.6 = ‘0’). Synchronous reception is stopped by clearing bit S1REN. -
Page 267: Xasc Interrupt Control
UM0404 XBUS asynchronous / synchronous serial interface An auto-reload of the timer with the content of the reload register is performed each time XS1BG is written to. However, if S1R = ‘0’ at the time the write operation to XS1BG is performed, the timer will not be reloaded until the first instruction cycle after S1R = ‘1’. - Page 268 XBUS asynchronous / synchronous serial interface UM0404 XPxIC registers (x = 0, 1, 2, 3). In particular, the four interrupt lines are available on the following interrupt vectors: • ReceiveXP0INTXP1INTXP2INT • TransmitXP0INTXP1INTXP2INT • Transmit BufferXP0INTXP1INTXP2INT • ErrorXP3INT Refer to Section 5.7: X-peripheral interrupt on page 117 for details.
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Page 269: Figure 110. Xasc Interrupt Generation
UM0404 XBUS asynchronous / synchronous serial interface Figure 110. XASC interrupt generation TBIR TBIR TBIR Idle Idle Asynchronous Mode TBIR TBIR TBIR Idle Idle Synchronous Mode DocID13284 Rev 2 269/564... -
Page 270: High-Speed Synchronous Serial Interface
High-speed synchronous serial interface UM0404 High-speed synchronous serial interface The high-speed synchronous serial interface SSC provides flexible high-speed serial communication between the ST10F276 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). -
Page 271: Figure 111. Sfrs And Port Pins Associated With The Ssc
UM0404 High-speed synchronous serial interface Figure 111. SFRs and port pins associated with the SSC Ports & Direction Control Alternate Functions Data Registers ODP3 E SSCBR E - Y - - Y Y - - - - - - - - SSCTB E Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - Y -... -
Page 272: Figure 112. Synchronous Serial Channel Ssc Block Diagram
High-speed synchronous serial interface UM0404 Figure 112. Synchronous serial channel SSC block diagram Slave Clock SCLK Baud Rate Generator Clock Control Clock P3.13 Master Clock Shift Clock Receive Interrupt Request SSC Control Transmit Interrupt Request Block Error Interrupt Request Status Control MTSR P3.9... - Page 273 UM0404 High-speed synchronous serial interface Function (programming mode, SSCEN = ‘0’) SSC Data Width Selection SSCBM Reserved. Do not use this combination. 1...15: Transfer Data Width is 2...16-bit [(SSCBM)+1] SSC Heading Control bit SSCHB Transmit/Receive LSB First Transmit/Receive MSB First SSC Clock Phase Control bit SSCPH Shift transmit data on the leading clock edge, latch on trailing edge...
- Page 274 High-speed synchronous serial interface UM0404 Function (operating mode, SSCEN = ‘1’) SSC bit Count Field SSCBC Shift counter is updated with every shifted bit. Do not write to SSC Transmit Error Flag SSCTE Transfer starts with the slave’s transmit buffer not being updated SSC Receive Error Flag SSCRE Reception completed before the receive buffer was read...
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Page 275: Full-Duplex Operation
UM0404 High-speed synchronous serial interface This allows the adaptation of the SSC to a wide range of applications, where serial data transfer is required. The data width selection supports the transfer of frames of any length, from 2 bit “characters” up to 16 bit “characters”. Starting with the LSB (SSCHB = ‘0’) allows communication with ASC0 devices in synchronous mode like serial interfaces. -
Page 276: Figure 113. Serial Clock Phase And Polarity Options
High-speed synchronous serial interface UM0404 Figure 113. Serial clock phase and polarity options Serial Clock SSCPO SSCPH SCLK Pins MTSR / MRST First Last Transmit Data Latch Data Shift Data Figure 114. SSC full duplex configuration Master Device #2 Slave Device #1 Shift Register Shift Register... - Page 277 UM0404 High-speed synchronous serial interface The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration. During a transfer each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: Only one slave drives the line, it enables the driver of its MRST pin.
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Page 278: Half Duplex Operation
High-speed synchronous serial interface UM0404 (SSCPO = ‘0’) will drive the alternate data output and (via the AND) the port pin SCLK immediately low. To avoid this, use the following sequence: • Select the clock idle level (SSCPO = ‘x’) •... -
Page 279: Port Control
UM0404 High-speed synchronous serial interface Figure 115. SSC half duplex configuration Device #2 Slave Master Device #1 Shift Register Shift Register MTSR MTSR MRST MRST Clock Clock Clock Common Transmit/ Device #3 Slave Receive Line Shift Register MTSR MRST Clock Continuous transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data. -
Page 280: Baud Rate Generation
High-speed synchronous serial interface UM0404 I/O operation, the respective port latches have to be set to '1', since the port latch outputs and the alternate output lines are ANDed. When an alternate data output line is not used (function disabled), it is held at a high level, allowing I/O operations via the port latch. The direction of the port lines depends on the operating mode. -
Page 281: Error Detection Mechanisms
UM0404 High-speed synchronous serial interface SSCBR (F0B4h / 5Ah) ESFR Reset Value: 0000h Baud Rate 12.4 Error detection mechanisms The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes, while Transmit Error and Baud rate Error only apply to slave mode. When an error is detected, the respective error flag is set. -
Page 282: Ssc Interrupt Control
High-speed synchronous serial interface UM0404 that slaves not selected for transmission only shift out ones, so their transmit buffers must be loaded with 'FFFFh' prior to any transfer. Note: A slave with push-pull output drivers, which is not selected for transmission, will normally have its output drivers switched. - Page 283 UM0404 High-speed synchronous serial interface SSCTIC (FF72h / B9h) Reset Value: - - 00h ILVL GLVL SSCRIC (FF74h / BAh) Reset Value: - - 00h ILVL GLVL SSCEIC (FF76h / BBh) Reset Value: - - 00h ILVL GLVL Note: Refer to Section 5.1.3: Interrupt control registers on page 100 for an explanation of the control fields.
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Page 284: Xbus High-Speed Synchronous Serial Interface
XBUS high-speed synchronous serial interface UM0404 XBUS high-speed synchronous serial interface A second High-Speed Synchronous Serial Interface (XSSC) is implemented on ST10F276. It is mapped on XBUS interface (Address range 00’E800h-00’E8FFh) and provides flexible high-speed serial communication between the ST10F276 and other microcontrollers, microprocessors or external peripherals. -
Page 285: Figure 117. Xbus Registers And Port Pins Associated With The Xssc
UM0404 XBUS high-speed synchronous serial interface Figure 117. XBUS registers and port pins associated with the XSSC Ports & Direction Control Alternate Functions Data Registers XSSCPORT XSSCBR XSSCTB Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y XSSCRB Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Control Registers... -
Page 286: Figure 118. Synchronous Serial Channel Xssc Block Diagram
XBUS high-speed synchronous serial interface UM0404 Figure 118. Synchronous serial channel XSSC block diagram Slave Clock SCLK1 Baud Rate Generator Clock Control Clock P6.5 Master Clock Shift Clock Receive Interrupt Request XSSC Control Transmit Interrupt Request Block Error Interrupt Request Status Control MTSR1... - Page 287 UM0404 XBUS high-speed synchronous serial interface Function (programming mode, SSCEN = ‘0’) XSSC Clock Phase Control bit SSCPH Shift transmit data on the leading clock edge, latch on trailing edge Latch receive data on leading clock edge, shift on trailing edge XSSC Clock Polarity Control bit SSCPO Idle clock line is low, leading clock edge is low-to-high transition...
- Page 288 XBUS high-speed synchronous serial interface UM0404 Function (operating mode, SSCEN = ‘1’) XSSC Baud rate Error Flag SSCBE More than factor 2 or 0.5 between Slave’s actual and expected Baud rate SSCBSY XSSC Busy Flag: Set while a transfer is in progress. Do not write to XSSC Master Select bit SSCMS Slave Mode.
- Page 289 UM0404 XBUS high-speed synchronous serial interface XSSCTB (E806h) XBUS Reset Value: 0000h XSSCRB (E808h) XBUS Reset Value: xxxxh It is moved to the shift register as soon as this is empty. An XSSC-master (SSCMS = ‘1’) immediately begins transmitting, while an XSSC-slave (SSCMS = ‘0’) will wait for an active shift clock.
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Page 290: Full-Duplex Operation
XBUS high-speed synchronous serial interface UM0404 13.1 Full-duplex operation The different devices are connected through three lines. The definition of these lines is always determined by the master: The line connected to the master's data output pin MTSR1 is the transmit line, the receive line is connected to its data input line MRST1, and the clock line is connected to pin SCLK1. -
Page 291: Figure 120. Xssc Full Duplex Configuration
UM0404 XBUS high-speed synchronous serial interface Figure 120. XSSC full duplex configuration Master Device #2 Slave Device #1 Shift Register Shift Register Transmit MTSR1 MTSR1 Receive MRST1 MRST1 Clock Clock Clock Device #2 Slave Shift Register MTSR1 MRST1 Clock The data output pins MRST1 of all slave devices are connected together onto the one receive line in this configuration. - Page 292 XBUS high-speed synchronous serial interface UM0404 which it expects data either by separate select lines, or by sending a special command to this slave. After performing all necessary initialization of the XSSC, the serial interfaces can be enabled. For a master device, the alternate clock line will now go to its programmed polarity. The alternate data line will go to either '0' or '1', until the first transfer will start.
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Page 293: Half Duplex Operation
UM0404 XBUS high-speed synchronous serial interface 13.2 Half duplex operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both pins MTSR1 and MRST1 of each device, the clock line is connected to the SCLK1 pin. -
Page 294: Port Control
XBUS high-speed synchronous serial interface UM0404 Continuous transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer XSSCTB is empty and ready to be loaded with the next transmit data. If XSSCTB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay. -
Page 295: Error Detection Mechanisms
UM0404 XBUS high-speed synchronous serial interface The Baud rate generator is clocked by f /2. The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register XSSCCON. Register XSSCBR is the dual-function Baud Rate Generator/Reload register. Reading XSSCBR, while the XSSC is enabled, returns the content of the timer. -
Page 296: Xssc Interrupt Control
XBUS high-speed synchronous serial interface UM0404 via SSCBEN, the error interrupt request flag (see XP3INT line). Using this error detection capability requires that the slave's Baud rate generator is programmed to the same Baud rate as the master device. This feature detects false additional, or missing pulses on the clock line (within a certain frame). -
Page 297: Watchdog Timer
UM0404 Watchdog timer Watchdog timer The watchdog timer (WDT) provides recovery from software or hardware failure. If the software fails to service this timer before an overflow occurs, an internal reset sequence is initiated. This internal reset will also pull the RSTOUT pin low, this resets the peripheral hardware which might have caused the malfunction. -
Page 298: Operation Of The Watchdog Timer
Watchdog timer UM0404 14.1 Operation of the watchdog timer The current count value of the watchdog timer is contained in the Watchdog Timer Register WDT, which is a bit-addressable read-only register. The operation of the Watchdog Timer is controlled by its bit-addressable Watchdog Timer Control Register WDTCON. This register specifies the reload value for the high byte of the timer, selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow. -
Page 299: Table 42. Wdtcon Bits Value On Different Resets
UM0404 Watchdog timer A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active (low) after the programmed wait-states. Otherwise the external bus cycle will be aborted. After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled. -
Page 300: Table 43. Wdtrel Reload Value
Watchdog timer UM0404 The time period for an overflow of the watchdog timer is programmable in two ways: • The input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON to be either f / 2 or f / 128. - Page 301 UM0404 Watchdog timer Table 44. Reset events summary (continued) RSTIN WDTCON Flags Event Synch. max (4TCL, 500ns) 1032TCL Synch. max (4TCL, 500ns) 1032TCL max (4TCL, 500ns) 1032TCL Short hardware reset Synch. (Synchronous) Activated by internal logic for 1024TCL max (4TCL, 500ns) 1032TCL Synch.
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Page 302: The Bootstrap Loader
Alternate Boot Mode: jump to address 09’0000h • Selective Bootstrap Loader: jump to a predefined location in Test-Flash (controlled by ST) and check which communication channel is selected • User code: make a software reset and jump to 00’0000h 302/564... -
Page 303: Standard Bootstrap Loader
UM0404 The bootstrap loader Table 45. ST10F276x boot mode selection P0.5 P0.4 ST10 decoding User Mode: user Flash mapped at 00’0000h Standard Bootstrap Loader: User Flash mapped from 00’0000h, code fetches redirected to Test-Flash at 00’0000h Alternate Boot Mode: Flash mapping depends on signatures integrity check Reserved 15.2... -
Page 304: Figure 124. St10F276X New Standard Bootstrap Loader Program Flow
The bootstrap loader UM0404 Figure 124. ST10F276x new standard bootstrap loader program flow START Falling-edge on Falling-edge on UART0 RxD? CAN1 RxD? UART BOOT Start Timer PT0 Start Timer T6 UART RxD = 0? UART0 RxD = 1? Stop Timer T6 CAN1 RxD = 1? Initialize UART Send Acknowledge... -
Page 305: St10 Configuration In Bsl
UM0404 The bootstrap loader 15.2.2 ST10 configuration in BSL When the ST10F276 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked in bold): Watchdog Timer Disabled Register SYSCON: 0404 XPEN bit set for Bootstrap via ;... -
Page 306: Hardware To Activate Bsl
The bootstrap loader UM0404 when ST10F276 is reset with P0L.4 low. After loading a preselected number of bytes, ST10F276 begins executing the downloaded program. The First level user code run on ST10F276. Typically, this first level user code is another loader that is used to download the application software into the ST10F276. The loaded application software is now running. -
Page 307: Memory Configuration In Bootstrap Loader Mode
UM0404 The bootstrap loader Figure 126. Hardware provisions to activate the BSL External Signal Normal Boot P0L.4 P0L.4 P0L.4 8kΩ max. P0L.4 8kΩ max. Circuit 2 Circuit 1 15.2.5 Memory configuration in bootstrap loader mode The configuration (that is, the accessibility) of the ST10F276’s memory areas after reset in Bootstrap Loader mode differs from the standard case. -
Page 308: Loading The Start-Up Code
The bootstrap loader UM0404 Figure 127. Memory configuration after reset 16 Mbytes 16 Mbytes 16 Mbytes access to access to external external Depends on reset config. (EA, P0) enabled disabled int. int. int. access to access to Depends on int. Flash int. -
Page 309: Hardware Requirements
UM0404 The bootstrap loader from location 00’0000 of the internal Flash (User Flash) or the external memory, as programmed via pin EA. Note: If a bidirectional Software Reset is executed, and external memory boot is selected (EA = 0), a degeneration of the Software Reset event into a Hardware Reset can occur (Refer to section for details). -
Page 310: Entering Bootstrap Via Uart
The bootstrap loader UM0404 Figure 128. UART bootstrap loader sequence RSTIN P0L.4 RxD0 TxD0 CSP:IP 32 bytes Int. Boot ROM / Test-Flash BSL-routine user software 1) BSL initialization time, > 1ms @ f = 40 MHz. 2) Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host. 3) Acknowledge byte, sent by ST10F276. -
Page 311: Loading The Start-Up Code
UM0404 The bootstrap loader Watchdog Timer: Disabled Register SYSCON: 0400 Context Pointer CP: FA00 Register STKUN: FA00 Stack Pointer SP: FA40 Register STKOV: FC00 Register BUSCON0: according to startup configuration Register S0CON: 8011 Register BUSCON0: according to startup configuration Register S0BG: according to ‘00’... -
Page 312: Choosing The Baud Rate For The Bsl Via Uart
The bootstrap loader UM0404 15.3.5 Choosing the baud rate for the BSL via UART The calculation of the serial baudrate for ASC0 from the length of the first zero byte that is received, allows the operation of the bootstrap loader of the ST10F276 with a wide range of baudrates. -
Page 313: Standard Bootstrap With Can
UM0404 The bootstrap loader Higher baudrates, however, may be used as long as the actual deviation does not exceed the limit. A certain baudrate (marked I) in Figure 129 may for example, violate the deviation limit, while an even higher baudrate (marked II) in Figure 129 stays very well below it. -
Page 314: Entering The Can Bootstrap Loader
The bootstrap loader UM0404 15.4.2 Entering the CAN bootstrap loader The ST10F276 enters BSL mode, if pin P0L.4 is sampled low at the end of a hardware reset. In this case the built-in bootstrap loader is activated independent of the selected bus mode. -
Page 315: St10 Configuration In Can Bsl
UM0404 The bootstrap loader 15.4.3 ST10 configuration in CAN BSL When the ST10F276 has entered BSL mode via CAN, the following configuration is automatically set (values that deviate from the normal reset values, are marked in bold): Watchdog Timer: Disabled Register SYSCON: 0404 ;... -
Page 316: Choosing The Baudrate For The Bsl Via Can
The bootstrap loader UM0404 This second level of loaded code may be the final application code. It may also be another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data. It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory. -
Page 317: Table 46. Ranges Of Timer Contents Versus Brp Value
UM0404 The bootstrap loader Therefore the maximum error at the detection of the communication on CAN pin is: (1 not taken + 1 taken jumps) + 1 taken jump + 1 bit set: (6) + 6 CPU clock cycles The error at the detection for the 5th recessive bit is: (1 taken jump) + 1 not taken jump + 1 compare + 1 bit clear: (4) + 6 CPU cycles In the worst case the induced error is of six CPU clock cycles. -
Page 318: How To Compute The Baud Rate Error
The bootstrap loader UM0404 To have a better precision, the target is to have the smallest BRP so that the time quantum is the smallest possible. Thus an error on the calculation of time quanta in a bit time is minored. -
Page 319: Bootstrap Via Can
UM0404 The bootstrap loader Note: In most cases (24 MHz, 32 MHz, 40 MHz of CPU frequency and 125, 250, 500 or 1 Mbit/s of bitrate) there is no error. Anyway, it is better to check the error with the real application parameters. -
Page 320: Hardware Aspects
The bootstrap loader UM0404 is not in the bootstrap loader code), the settings can be modified. The following steps must be performed in order to do this: • disable the XPeripherals by clearing XPEN in SYSCON register. Attention: this part of code must not be located in XRAM as it will be disabled. -
Page 321: St10 Configuration In Alternate Boot Mode
UM0404 The bootstrap loader 15.6.4 ST10 configuration in alternate boot mode When the ST10F276 has entered BSL mode via CAN, the following configuration is automatically set (values that deviate from the normal reset values, are marked in bold): Watchdog Timer: Disabled Register SYSCON: 0404... -
Page 322: Alternate Boot User Software
The bootstrap loader UM0404 15.6.7 Alternate boot user software If the rules described here before are met (that is,: mapping of variables, disabling of interrupts, exit conditions, predefined vectors in Block 0 of Bank 2, Watchdog usage) then users can write the software they want to execute in this mode starting from 09’0000h. 15.6.8 User/alternate mode signature integrity check The behavior of the Alternate Boot Mode is based on the computing of a signature between... -
Page 323: Internal Decoding Of Test Modes
Alternate Boot Mode decoding: (P0L.5 & P0L.4) • Standard Bootstrap decoding: (P0L.5 & P0L.4) • Normal operation: (P0L.5 & P0L.4) The other configurations select ST internal test modes. 15.6.12 Example In the following example Alternate Boot Mode works as follow: •... - Page 324 The bootstrap loader UM0404 Function UART Selection ‘0’: UART will not be watched for a Start condition. ‘1’: UART will be watched for a Start condition. CAN1 Selection ‘0’: CAN1 will not be watched for a Start condition. ‘1’: CAN1 will be watched for a Start condition. Reserved 2..7 For upward compatibility, must be programmed to ‘0’...
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Page 325: Figure 132. Reset Boot Sequence
Standard Start No (P0L[5..4] = ‘11’) Yes (P0L[5..4] = ‘01’) Boot Mode? Yes (P0L[5..4] = ‘10’) No (P0L[5..4] = ‘other config.’) ST Test Modes Software Checks K1 is OK User Reset Vector (K1 is OK?) K1 is not OK Software Checks... -
Page 326: The Capture / Compare Units
The capture / compare units UM0404 The capture / compare units The ST10F276 provides two, almost identical, Capture / Compare (CAPCOM) units, which differ only in the way they are connected to the I/O pins. They provide 32 channels which interact with 4 timers. -
Page 327: Figure 133. Sfrs And Port Pins Associated With The Capcom Units
UM0404 The capture / compare units Figure 133. SFRs and Port Pins associated with the CAPCOM units DocID13284 Rev 2 327/564... - Page 328 The capture / compare units UM0404 A CAPCOM unit handles high speed I/O tasks such as pulse and waveform generation, pulse width modulation, or recording of the time at which specific events occur. It also allows the implementation of up to 16 software timers. The maximum resolution of the CAPCOM units is calculated with the formula in Section 16.1: CAPCOM timers on page 329 and is...
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Page 329: Capcom Timers
UM0404 The capture / compare units Figure 134. CAPCOM unit block diagram Reload Register TxREL x = 0, 7 n = 3...10 Clock Interrupt Request Input CAPCOM Timer Tx TxIN Control GPT2 Timer T6 Over / Underflow Mode Control Sixteen 16-bit Capture inputs (Capture (Capture/Compare) -
Page 330: Figure 135. Block Diagram Of Capcom Timers T0 And T7
The capture / compare units UM0404 Figure 135. Block diagram of CAPCOM timers T0 and T7 Reload Register TxREL Input Control Clock GPT2 Timer T6 Interrupt CAPCOM Timer Tx TxIR Over / Underflow Request Edge Select Txl TxM TxIN x = 0, 7 Figure 136. - Page 331 UM0404 The capture / compare units Function Timer / Counter x Input Selection [(TxI)+3] Timer Mode (TxM ‘0’) Input Frequency = f See also table below for examples. Counter Mode (TxM ‘1’): X00 Overflow / Underflow of GPT2 Timer 6 X01 Positive (rising) edge on pin TxIN X10 Negative (falling) edge on pin TxIN X11 Any edge (rising and falling) on pin TxIN...
- Page 332 The capture / compare units UM0404 Timer input selection TxI 000b 001b 010b 011b 100b 101b 110b 111b Pre-scaler for f 1024 Resolution in 1024 CPU clock cycles Refer to the device datasheet for a table of timer input frequencies, resolution and periods for each pre-scaler option in TxI.
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Page 333: Capcom Unit Timer Interrupts
UM0404 The capture / compare units The reload registers TxREL are not bit-addressable. 16.2 CAPCOM unit timer interrupts Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective timer will be set. This flag can be used to generate an interrupt or trigger a PEC service request, when enabled by the respective interrupt enable bit TxIE. - Page 334 The capture / compare units UM0404 When capture or compare operation is disabled for one of the CCx registers, it may be used for general purpose variable storage. The functions of the 32 capture / compare registers are controlled by the eight mode control registers named CCM0...CCM7 which are all organized identically (see description below).
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Page 335: Selection Of Capture Modes And Compare Modes
UM0404 The capture / compare units CCM6 (FF26h / 93h) Reset Value: 0000h ACC27 CCMOD27 ACC26 CCMOD26 ACC25 CCMOD25 ACC24 CCMOD24 CCM7 (FF28h / 94h) Reset Value: 0000h ACC31 CCMOD31 ACC30 CCMOD30 ACC29 CCMOD29 ACC28 CCMOD28 Function Mode Selection for Capture / Compare Register CCx CCMODx The available capture / compare modes are listed in the table below. -
Page 336: Capture Mode
The capture / compare units UM0404 16.4 Capture mode In response to an external event the content of the associated timer (T0 / T1 or T7 / T8, depending on the used CAPCOM unit and the state of the allocation control bit ACCx) is latched into the respective capture register CCx. -
Page 337: Compare Mode 0
UM0404 The capture / compare units As for capture mode, the compare registers are also processed sequentially during compare mode. When any two compare registers are programmed to the same compare value, their corresponding interrupt request flags will be set to '1' and the selected output signals will be generated within eight CPU clock cycles after the allocated timer is incremented to the compare value. -
Page 338: Compare Mode 1
The capture / compare units UM0404 Figure 138. Compare mode 0 and 1 block diagram Interrupt CCxIR Capture Register CCx Request CCxIO Comparator Port Latch Toggle (Mode 1) CCMODx Interrupt Input CAPCOM Timer Ty TyIR Request Clock x = 31...0 y = 0, 1, 7, 8 Note: The port latch and pin remain unaffected in compare mode 0. -
Page 339: Compare Mode 2
UM0404 The capture / compare units On channels 24...27 compare mode 1 will generate interrupt requests but no output function is provided. Figure 139. Timing example for compare modes 0 and 1 Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value <TyREL>... -
Page 340: Compare Mode 3
The capture / compare units UM0404 Figure 140. Compare mode 2 and 3 block diagram Interrupt Capture Register CCx CCxIR Request Comparator CCxIO Port Latch (Mode 3) Reset CCMODx Interrupt Input CAPCOM Timer Ty TyIR Request Clock x = 31...0 y = 0, 1, 7, 8 Note: The port latch and pin remain unaffected in compare mode 2. -
Page 341: Double Register Compare Mode
UM0404 The capture / compare units match was detected, the compare register is reloaded with a new value, this value will not become effective until the next timer period. In order to use the respective port pin as compare signal output pin CCxIO for compare register CCx in compare mode 3 this port pin must be configured as output and the corresponding direction control bit must be set to ‘1’. -
Page 342: Figure 142. Double Register Compare Mode Block Diagram
The capture / compare units UM0404 The double-register compare mode can be programmed individually for each register pair. In order to enable double-register mode the respective bank 1 register (see Table 50) must be programmed to compare mode 1 and the corresponding bank 2 register (see Table must be programmed to compare mode 0. -
Page 343: Capture / Compare Interrupts
UM0404 The capture / compare units The pins CCzIO (which are not selected for double-register compare mode) may be used for general purpose I/O. Figure 143. Timing example for double register compare mode Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value <TyREL>... -
Page 344: Table 51. Capcom Unit Interrupt Control Register Addresses
The capture / compare units UM0404 Table 51. CAPCOM unit interrupt control register addresses CAPCOM1 unit CAPCOM2 unit Register Register Register Address Register Address space space CC0IC FF78h / BCh CC16IC F160h / B0h ESFR CC1IC FF7Ah / BDh CC17IC F162h / B1h ESFR CC2IC... -
Page 345: Pulse Width Modulation Module
UM0404 Pulse width modulation module Pulse width modulation module The Pulse Width Modulation (PWM) Module of the ST10F276 generates up to four independent PWM signals. The minimum PWM signal frequency depends on the width (16 bits) and the resolution (CLK/1 or CLK/64) of the PWM timers. The maximum PWM signal frequency assumes that the PWM output signal changes with every cycle of the respective timer. -
Page 346: Figure 144. Sfrs And Port Pins Associated With The Pwm Module
Pulse width modulation module UM0404 Figure 144. SFRs and port pins associated with the PWM module Ports & Direction Control Alternate Functions Data Registers ODP7 E PP0 E - - - - - - - Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y - - - - - - - Y Y Y Y PP1 E Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y... -
Page 347: Operating Modes
UM0404 Pulse width modulation module Figure 145. PWM channel block diagram PPx Period Register Match Comparator Clock 1 Up/Down/ Input 16-bit Up/Down Counter Clear Control Control Clock 2 Match Comparator Output Control POUTx Enable Shadow Register Write Control x = 3...0 * User readable &... -
Page 348: Mode 1: Symmetrical Pwm Generation (Center Aligned Pwm)
Pulse width modulation module UM0404 The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register. This mechanism allows the selection of duty cycles from 0% to 100% including the boundaries. For a value of 0000h the output will remain at a high level, representing a duty cycle of 100%. -
Page 349: Burst Mode
UM0404 Pulse width modulation module Note that in mode 1 the period of the PWM signal is twice the period of the timer: PWM_Period = 2 x ([PPx] + 1) Mode1 Figure 147 illustrates the operation and output waveforms of a PWM channel in mode 1 for different values in the pulse width register. -
Page 350: Single Shot Mode
Pulse width modulation module UM0404 Figure 148. Operation and output waveform in burst mode Period Value Count Value Channel 0 Channel 1 Resulting Output POUT0 17.1.4 Single shot mode Single shot mode is selected by setting the respective bit PSx in register PWMCON1 to ‘1’. This mode is available for PWM channels 2 and 3. -
Page 351: Pwm Module Registers
UM0404 Pulse width modulation module Figure 149. Operation and output waveform in single shot mode Period=7 PTx Count Value PWx Pulse Width=4 Set PTRx Set PTRx PTRx Reset by Software by Software by Hardware for Next Pulse PTx stopped Period=7 PTx Count Value PWx Pulse... -
Page 352: Table 52. Pwm Frequencies
Pulse width modulation module UM0404 Up/down counters PTx Each counter PTx of a PWM channel is clocked either directly by the CPU clock or by the CPU clock divided by 64. Bit PTIx in register PWMCON0 selects the respective clock source. -
Page 353: Table 53. Pwm Module Channel Specific Register Addresses
UM0404 Pulse width modulation module This type of comparison allows a flexible control of the PWM signal. For the register locations refer to the Table Table 53. PWM module channel specific register addresses Register Address Reg. space Register Address Reg. space FE30h / 18h F030h / 18h ESFR... -
Page 354: Interrupt Request Generation
Pulse width modulation module UM0404 bit. The output signal of each PWM channel is individually enabled by bit PENx. If the output is not enabled the respective pin can be used for general purpose I/O and the PWM channel can only be used to generate an interrupt request. PWMCON1 (FF32h / 99h) Reset Value: 0000h PS3 PS2... -
Page 355: Pwm Output Signals
UM0404 Pulse width modulation module PWMIC (F17Eh / BFh) ESFR Reset Value: - - 00h ILVL GLVL Note: Refer to Section 5.1.3: Interrupt control registers on page 100 for an explanation of the control fields. 17.4 PWM output signals The output signals of the four PWM channels (POUT3...POUT0) are alternate output functions on Port7 (P7.3...P7.0). -
Page 356: Figure 150. Pwm Output Signal Generation
Pulse width modulation module UM0404 Figure 150. PWM output signal generation PWM 3 Pin P7.3 PWMCON1.PEN3 Latch P7.3 PWM 2 Pin P7.2 Latch P7.2 PWMCON1.PEN2 PWM 1 Pin P7.1 Latch P7.1 PWMCON1.PEN1 & PWM 0 Pin P7.0 Latch P7.0 PWMCON1.PEN0 PWMCON1.PB01 356/564 DocID13284 Rev 2... -
Page 357: Xbus Pulse Width Modulation Module
UM0404 XBUS pulse width modulation module XBUS pulse width modulation module A second Pulse Width Modulation (XPWM) Module is implemented on ST10F276. It is mapped on XBUS interface (Address range 00’EC00h-00’ECFFh) and generates up to four additional independent PWM signals. The minimum PWM signal frequency depends on the width (16 bits) and the resolution (CLK/1 or CLK/64) of the XPWM timers. -
Page 358: Figure 151. Xbus Registers And Port Pins Associated With The Xpwm Module
XBUS pulse width modulation module UM0404 Figure 151. XBUS registers and port pins associated with the XPWM module Ports & Direction Control Alternate Functions Data Registers XPWMPORT XPP0 XPW0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Counter Registers XPP1 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y... -
Page 359: Operating Modes
UM0404 XBUS pulse width modulation module Figure 152. XPWM channel block diagram XPPx Period Register Match Comparator Clock 1 XPTx Up/Down/ Input 16-bit Up/Down Counter Clear Control Control Clock 2 Match Comparator Output Control XPOUTx Enable Shadow Register Write Control x = 3...0 * User readable &... -
Page 360: Mode 1: Symmetrical Pwm Generation (Center Aligned Pwm)
XBUS pulse width modulation module UM0404 The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register. This mechanism allows the selection of duty cycles from 0% to 100% including the boundaries. For a value of 0000h the output will remain at a high level, representing a duty cycle of 100%. -
Page 361: Burst Mode
UM0404 XBUS pulse width modulation module XPWM_Period = 2 x ([XPPx] + 1) Mode1 Figure 147 illustrates the operation and output waveforms of a XPWM channel in mode 1 for different values in the pulse width register. This mode is referred to as Center Aligned PWM, because the value in the pulse width shadow register effects both edges of the output signal symmetrically. -
Page 362: Single Shot Mode
XBUS pulse width modulation module UM0404 Figure 155. Operation and output waveform in burst mode XPP0 Period Value XPT0 Count Value Channel 0 Channel 0 XPP1 XPT1 Channel 1 Resulting Output XPOUT0 18.1.4 Single shot mode Single shot mode is selected by setting the respective bit PSx in register XPWMCON1 to ‘1’. This mode is available for XPWM channels 2 and 3. -
Page 363: Xpwm Module Registers
UM0404 XBUS pulse width modulation module Figure 156. Operation and output waveform in single shot mode XPPx Period=7 XPTx Count Value XPWx Pulse Width=4 Set PTRx Set PTRx PTRx Reset by Software by Software by Hardware for Next Pulse XPTx stopped XPPx Period=7 XPTx Count... -
Page 364: Table 54. Xpwm Frequencies
XBUS pulse width modulation module UM0404 Up/down counters XPTx Each counter XPTx of a XPWM channel is clocked either directly by the CPU clock or by the CPU clock divided by 64. Bit PTIx in register XPWMCON0 selects the respective clock source. -
Page 365: Table 55. Xpwm Module Channel Specific Register Addresses
UM0404 XBUS pulse width modulation module This type of comparison allows a flexible control of the PWM signal. For the register locations refer to Table Table 55. XPWM module channel specific register addresses Register Address Reg. space Register Address Reg. space XPW0 EC30h XBUS... - Page 366 XBUS pulse width modulation module UM0404 XPWMCON0SET (EC06h) XBUS Reset Value: 0000h SET.15 SET.14 SET.13 SET.12 SET.11 SET.10 SET.9 SET.8 SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0 Function XPWMCON0 Bit Y Set SET.Y Writing a ‘1’ will set the corresponding bit in XPWMCON0 register. Writing a ‘0’...
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Page 367: Interrupt Request Generation
UM0404 XBUS pulse width modulation module Function XPWM Channel 0/1 Burst Mode Control bit PB01 ‘0’: Channels 0 and 1 work independently in respective standard mode ‘1’: Outputs of channels 0 and 1 are ANDed to POUT0 in burst mode XPWM Channel x Single Shot Mode Control bit ‘0’: Channel x works in respective standard mode ‘1’: Channel x operates in single shot mode... -
Page 368: Xpwm Output Signals
XBUS pulse width modulation module UM0404 also the common interrupt request line is asserted (XP2IR/XP3IR in registers XP2IC/XP3IC), provided that they are enabled via the common interrupt enable bits (XP2IE/XP3IE) and the dedicated enable bits inside XIRSEL2/XIRSEL3 registers. Note: The channel interrupt request flags (PIRx in register XPWMCON0) are not automatically cleared by hardware upon entry into the interrupt service routine, so they must be cleared via software. -
Page 369: Figure 157. Xpwm Output Signal Generation
UM0404 XBUS pulse width modulation module either to initialize the system or to react on some extraordinary condition, like a system fault or an emergency. Clearing the timer run bit PTRx stops the associated counter and leaves the respective output at its current level. The individual XPWM channel outputs are controlled by comparators according to the formula: PWM output signal = [XPTx] >... -
Page 370: Analog / Digital Converter
Analog / digital converter UM0404 Analog / digital converter The ST10F276 provides an analog / digital converter with 10-bit resolution and a sample & hold circuit on-chip. A multiplexer selects between up to 16+8 analog input channels (alternate functions of Port5 and Port1) either via software (fixed channel modes) or automatically (auto scan modes works automatically among the 16 channels of Port5, or among the 8 channels of Port1). -
Page 371: Figure 158. Sfrs, Xbus Registers And Port Pins Associated With The A/D Converter
UM0404 Analog / digital converter Figure 158. SFRs, XBUS registers and port pins associated with the A/D converter Ports & Direction Control Alternate Functions Data Registers ADDAT P5DIDIS Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y ADDAT2 E Y Y Y Y - - Y Y Y Y Y Y Y Y Y Y... -
Page 372: Mode Selection And Operation
Analog / digital converter UM0404 Figure 159. Analog / digital converter block diagram ADCMUX Open (*) AN23 ADCON P1L.7 ADCIR Conversion Interrupt Analog Control Requests Input ADEIR Channels AN16 P1L.0 Result Reg. ADDAT 10-Bit S + H Converter 32-16 16-1 Result Reg. - Page 373 UM0404 Analog / digital converter The analog input channels AN16...AN23 are alternate functions of Port1L which is an 8-bit bidirectional port. The Port1L lines may either be used as analog input or digital input/output. The additional register XP1DIDIS can be used to further protect ADC input analog section disabling the digital input section.
- Page 374 Analog / digital converter UM0404 Function ADCH ADC Analog Channel Input Selection ADC Mode Selection ’0 0’: Fixed Channel Single Conversion ’0 1’: Fixed Channel Continuous Conversion ’1 0’: Auto Scan Single Conversion ’1 1’: Auto Scan Continuous Conversion ADC Disable ‘0’: Analog circuitry of A/D converter is on: it can be used properly ADOFF ‘1’: Analog circuitry of A/D converter is turned off (no consumption): non conversion...
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Page 375: Fixed Channel Conversion Modes
UM0404 Analog / digital converter ADDAT2 (F0A0h / 50h) ESFR Reset Value: 0000h CHNR ADRES Function ADRES A/D Conversion Result (10 bits) Channel Number 4 bits, identifies the converted analog channel: first eight binary values should be CHNR combined with status of bit ADCMUX of register XMISC to distinguish between channel(7:0) and channel(23:16). -
Page 376: Auto Scan Conversion Modes
Analog / digital converter UM0404 In continuous conversion mode the converter will automatically start a new conversion of the channel specified in ADCH. ADCIR will be set after each completed conversion. When bit ADST is reset by software, while a conversion is in progress, the converter will complete the current conversion and then stop and reset bit ADBSY. -
Page 377: Wait For Addat Read Mode
UM0404 Analog / digital converter 19.1.3 Wait for ADDAT read mode If in default mode of the ADC a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete, the previous result in register ADDAT is lost because it is overwritten by the new value, and the A/D overrun error interrupt request flag ADEIR will be set. - Page 378 Analog / digital converter UM0404 otherwise the input multiplexer will switch to the new channel. It is recommended to only change the channel number with no injected conversion running (see Figure 162). A channel injection can be triggered in two ways: •...
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Page 379: Figure 162. Channel Injection Example
UM0404 Analog / digital converter Figure 162. Channel injection example Conversion #x-1 #x-2 #x-3 #x-4 #... of Channel: Write ADDAT #x-2 #x+1 #x-1 #x-3 #x-4 ADDAT Full #x+1 #x-1 #x-2 #x-3 #x-4 Read ADDAT Channel Injection Request by CC31 Injected Conversion Write ADDAT2 of Channel #y ADDAT2 Full... -
Page 380: Adc Power Off (Adoff)
Analog / digital converter UM0404 Figure 163. Channel injection example with wait for read #x-1 Conversion #x-2 #x-3 #... of Channel: Wait until ADDAT2 is read Write ADDAT #x+1 #x-1 #x-2 #x-3 ADDAT Full #x+1 #x-1 #x-2 #x-3 Read ADDAT Injected Conversion Channel Injection of Channel #y... -
Page 381: Conversion Timing Control
UM0404 Analog / digital converter at the end of the conversion (or sequence of conversions if Scan mode was selected), the ADC is switched off (as soon as ADBSY bit is cleared). When ADC is off (ADOFF bit set), setting bit ADST wakes automatically up the ADC and a conversion starts: the accuracy is unfortunately not yet granted, since the analog circuitry needs at least 50μs to complete the power-up transient phase. -
Page 382: A/D Converter Interrupt Control
Analog / digital converter UM0404 Table 56. ADC sampling and conversion timing Total ADCTC ADSTC Sample Comparison Extra conversion TCL * 120 TCL * 240 TCL * 28 TCL * 388 TCL * 140 TCL * 280 TCL * 16 TCL * 436 TCL * 200 TCL * 280... -
Page 383: Calibration
UM0404 Analog / digital converter ADEIC (FF9Ah / CDh) Reset Value: - - 00h ILVL GLVL Note: Refer to Section 5.1.3: Interrupt control registers on page 100 for explanation of the control fields. 19.4 Calibration A full calibration sequence is performed after a reset. This full calibration lasts 40.629 ± 1 CPU clock cycles. -
Page 384: Total Unadjusted Error
Analog / digital converter UM0404 Gain error combined with offset error, represents the so-called full-scale error (Figure 164, OFS + GE). Quantization error Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB. Non-linearity error Non-Linearity error is the deviation between actual and the best-fitting A/D conversion characteristics (see Figure... -
Page 385: Analog Reference Pins
UM0404 Analog / digital converter Figure 164. A/D conversion characteristic Offset Error OFS Gain Error GE Ideal Characteristic Bisector Characteristic Digital (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential Non-Linearity Error (DNL) (4) Integral Non-Linearity Error (INL) 1 LSB (ideal) 1018 1020... -
Page 386: Figure 165. A/D Converter Input Pins Scheme
Analog / digital converter UM0404 ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; besides, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). -
Page 387: Figure 166. Charge Sharing Timing Diagram During Sampling Phase
UM0404 Analog / digital converter assuming a conversion rate of 250 kHz, with C equal to 4pF, a resistance of 1MΩ is obtained (R = 1 / f , where f represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on C ) and the sum of R , the external circuit... - Page 388 Analog / digital converter UM0404 designed to be robust also in the very worst case: the sampling time T is always much longer than the internal time constant: τ < ⋅ << • The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance according to the following equation:...
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Page 389: Figure 167. Anti-Aliasing Filter And Conversion Rate
UM0404 Analog / digital converter Figure 167. Anti-aliasing filter and conversion rate Analog Source Bandwidth (V ≤ 2 R (Conversion Rate vs. Filter Pole) Noise (Anti-aliasing Filtering Condition) ≤ f (Nyquist) Anti-Aliasing Filter (f = RC Filter pole) Sampled Signal Spectrum (f = Conversion Rate) The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on C... -
Page 390: Example Of External Network Sizing
Analog / digital converter UM0404 19.5.4 Example of external network sizing The following hypothesis are formulated in order to proceed in designing the external network on A/D Converter input pins: • Analog Signal Source Bandwidth (f ): 10 kHz • Conversion Rate (f ): 25 kHz •... - Page 391 UM0404 Analog / digital converter accuracy error introduced by the switched capacitance equivalent resistance is in this case: -------------- - 10MΩ So the error due to the voltage partitioning between the real resistive path and C less then half a count (considering the worst case when V = 5V): ⋅...
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Page 392: I 2 C Interface
C interface UM0404 C interface The I C is enabled by setting XPEN, bit 2 of the SYSCON register and bit XI2CEN of XPERCON register. Once this is done, pins P4.4 and P4.7 becomes fully dedicated to I interface and all the other alternate functions are bypassed (external memory and CAN2 functions). -
Page 393: General Description
UM0404 C interface 20.2 General description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I C bus by a data pin (SDA) and by a clock pin (SCL). -
Page 394: Sda/Scl Line Control
C interface UM0404 The speed of the I C interface may be selected between Standard (0-100kHz) and Fast I (100-400kHz). 20.2.3 SDA/SCL line control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. -
Page 395: Functional Description
UM0404 C interface Figure 169. I C interface block diagram DATA REGISTER (I2CDR) DATA CONTROL DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTER 1 (I2COAR1) OWN ADDRESS REGISTER 2 (I2COAR2) CLOCK CONTROL CLOCK CONTROL REGISTER (I2CCCR1/2) CONTROL REGISTER (I2CCR) CONTROL LOGIC STATUS REGISTER 1 (I2CSR1) STATUS REGISTER 2 (I2CSR2) INTERRUPT... - Page 396 C interface UM0404 Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: •...
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Page 397: Master Mode
UM0404 C interface If it is a Start then the interface discards the data and waits for the next slave address on the bus. • AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. - Page 398 C interface UM0404 Master receiver Following the address transmission and after I2CSR1 and I2CCR registers have been accessed, the master receives bytes from the SDA line into the I2CDR register via the internal shift register. After each byte the interface generates in sequence: •...
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Page 399: Figure 170. Transfer Sequencing
UM0404 C interface Figure 170. Transfer sequencing 7-bit Slave receiver: Address Data1 Data2 DataN ..7-bit Slave transmitter: Address Data1 Data2 DataN ..EV3-1 7-bit Master receiver: Address Data1 Data2 DataN ..7-bit Master transmitter: Address Data1 Data2 DataN ..10-bit Slave receiver: Header Address... -
Page 400: Interrupts
C interface UM0404 EV3-1 1, AF 1, BTF 1; AF is cleared by reading I2CSR2 register. BTF is cleared by releasing the lines (STOP 1, STOP 0) or by writing I2CDR register (I2CDR FFh). Note: If lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen. 1, STOPF 1, cleared by reading I2CSR2 register. -
Page 401: Table 57. Interrupt Event Summary
UM0404 C interface Table 57. Interrupt event summary Line Interrupt event Event flag 10-bit Address Sent Event (Master mode) ADD10 Start Bit Generation Event (Master mode) Address Matched Event (Slave mode) ADSL Address Byte Transmission Event (Master Mode) ENDAD Error Acknowledge Failure Event Stop Detection Event (Slave mode) STOPF... - Page 402 C interface UM0404 When interruptible Power Down mode is entered, I C SCL line (P4.4) can be used to wake- up the device from low power mode without resetting it, restarting the application from where it was stopped at the execution of PWRDN instruction. Again, refer to Section 5.6.1: Fast external interrupts on page 115 for further details.
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Page 403: Register Description
UM0404 C interface 20.5 Register description I2CCR (EA00h) XBUS Reset Value: 0000h – ENGC START ACK STOP Function Interrupt Enable This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE ‘0’: Interrupts disabled. ‘1’: Interrupts enabled. - Page 404 C interface UM0404 Function Enable General Call This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE 0). The 00h General Call address is acknowledged (01h ENGC ignored). ‘0’: General Call disabled. ‘1’: General Call enabled.
- Page 405 UM0404 C interface Function Byte transfer finished This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE = 1. It is cleared by software reading I2CSR1 register followed by a read or write of I2CDR register. It is also cleared by hardware when the interface is disabled (PE = 0).
- Page 406 C interface UM0404 I2CSR2 (EA04h) XBUS Reset Value: 0000h – ENDAD STOPF ARLO BERR GCAL Function General Call (Slave mode) This bit is set by hardware when a general call address is detected on the bus while ENGC 1. It is cleared by hardware detecting a Stop condition (STOPF 1) or GCAL when the interface is disabled (PE...
- Page 407 UM0404 C interface Function Acknowledge Failure This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE 1. It is cleared by software by reading I2CSR2 register or by hardware when the interface is disabled (PE The SCL line is not held low while AF ‘0’: No acknowledge failure ‘1’: Acknowledge failure...
- Page 408 C interface UM0404 Function Address direction bit This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when ADD0 the interface is disabled (PE Note: Address 01h is always ignored. Interface address ADD(7:1) These bits define the I C bus address of the interface.
- Page 409 UM0404 C interface Function 8-bit Data Register These bits contain the received byte or the byte to be transmitted on the bus. – Transmitter mode: Byte transmission starts automatically when the software D(7:0) writes in the I2CDR register. – Receiver mode: The first data byte is received automatically in the I2CDR register using the least significant bit of the address.
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Page 410: Can Modules
CAN modules UM0404 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part A and B (active). The module is based on C-CAN module characteristics. The following system resources are used to interface the module with the ST10 core: •... -
Page 411: Table 58. Can1 Register Mapping
UM0404 CAN modules Table 58. CAN1 register mapping Reset Name Physical address Description value CAN1CR EF00h CAN1: CAN Control Register 0001h CAN1SR EF02h CAN1: Status Register 0000h CAN1EC EF04h CAN1: Error Counter 0000h CAN1BTR EF06h CAN1: Bit Timing Register 2301h CAN1IR EF08h CAN1: Interrupt Register... -
Page 412: Table 59. Can2 Register Mapping
CAN modules UM0404 Table 58. CAN1 register mapping (continued) Reset Name Physical address Description value CAN1IP2 EFA2h CAN1: Interrupt Pending 2 0000h CAN1MV1 EFB0h CAN1: Message Valid 1 0000h CAN1MV2 EFB2h CAN1: Message Valid 2 0000h Table 59. CAN2 register mapping Reset Name Physical address... -
Page 413: Interrupt
UM0404 CAN modules Table 59. CAN2 register mapping Reset Name Physical address Description value CAN2IF2DB1 EE52h CAN2: IF2 Data B 1 0000h CAN2IF2DB2 EE54h CAN2: IF2 Data B 2 0000h CAN2TR1 EE80h CAN2: Transmission Request 1 0000h CAN2TR2 EE82h CAN2: Transmission Request 2 0000h CAN2ND1 EE90h... -
Page 414: Configuration Examples
CAN modules UM0404 Note: CAN Parallel mode is effective only if both CAN1 and CAN2 are enabled through the setting of bits CAN1EN and CAN2EN in XPERCON register. If CAN1 is disabled, CAN2 remains on P4.4/P4.7 even if bit CANPAR is set. XMISC (EB46h) XBUS Reset Value: 0000h... -
Page 415: Figure 172. Connection To Single Can Bus Via Separate Can Transceivers
UM0404 CAN modules Figure 172. Connection to single CAN bus via separate CAN transceivers XMISC.CANPAR = 0 CAN1 CAN2 2.7kΩ 2.7kΩ P4.5 P4.6 P4.4 P4.7 Transceiver Transceiver CAN_H CAN bus CAN_L Figure 173. Connection to single CAN bus via one common transceiver XMISC.CANPAR = 0 CAN1 CAN2... -
Page 416: Clock Prescaling
CAN modules UM0404 Figure 174. Connection to two different CAN buses (e.g. for gateway application) XMISC.CANPAR = 0 CAN1 CAN2 2.7kΩ 2.7kΩ P4.5 P4.6 P4.4 P4.7 Transceiver Transceiver CAN_H CAN_H CAN_L CAN_L CAN bus 1 CAN bus 2 Figure 175. Connection to one CAN bus with internal parallel mode enabled XMISC.CANPAR = 1 (Both CAN enabled) CAN1... -
Page 417: Can Module: Functional Overview
UM0404 CAN modules baudrate defined by the protocol standard. On the other hand, the CPU frequency can be reduced down to 8 MHz: providing the CAN module directly with the CPU clock disabling the prescaler factor, it is still possible to obtain the maximum CAN speed (1Mbaud). After reset the prescaler is enabled, so CPU clock is divided by 2 and then provided to the CAN modules: according to the system clock frequency, the application can disable the prescaler to obtain the required baudrate. -
Page 418: Block Diagram
CAN modules UM0404 21.6 Block diagram The module consists of the following functional blocks (see Figure 176): • CAN Core: CAN Protocol Controller and Rx/Tx Shift Register for serial/parallel conversion of messages. • Message RAM: Stores Message Objects and Identifier Masks. •... -
Page 419: Can Message Transfer
UM0404 CAN modules Access to the Bit Timing Register and to the BRP Extension Register for the configuration of the bit timing is enabled when both bits Init and CCE in the CAN Control Register are set. Resetting Init (by CPU only) finishes the software initialization. Afterwards the Bit Stream Processor BSP (see Section 21.9.10: Configuration of the bit timing) synchronizes itself to... -
Page 420: Test Mode
CAN modules UM0404 The Disabled Automatic Retransmission mode is enabled by programming bit DAR in the CAN Control Register to one. In this operation mode the programmer has to consider the different behavior of bits TxRqst and NewDat in the Control Registers of the Message Buffers: •... -
Page 421: Loop Back Combined With Silent Mode
UM0404 CAN modules messages and stores them (if they pass acceptance filtering) into a Receive Buffer. Figure 178 shows the connection of signals CAN_TxD and CAN_RxD to the CAN Core in Loop Back Mode. Figure 178. CAN core in loop back mode CAN_TxD CAN_RxD C-CAN •... -
Page 422: Basic Mode
CAN modules UM0404 21.7.8 Basic mode The CAN Core can be set in Basic Mode by programming the Test Register bit Basic to one. In this mode the C-CAN module runs without the Message RAM. The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is requested by writing the Busy bit of the IF1 Command Request Register to one. -
Page 423: Table 60. C-Can Register Memory Space Summary
UM0404 CAN modules The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message reception/transmission. Table 60. -
Page 424: Hardware Reset Description
CAN modules UM0404 Table 60. C-CAN register memory space summary Address Name Reset value Note CAN Base + 0xB0 Message Valid 1 0x0000 read only CAN Base + 0xB2 Message Valid 2 0x0000 read only CAN Base + 0xB4 - 0xBE — reserved —... - Page 425 UM0404 CAN modules Function Error Interrupt Enable ‘0’: Disabled - No Error Status Interrupt will be generated. ‘1’: Enabled - A change in the bits BOff or EWarn in the Status Register will generate an interrupt. Disable Automatic Retransmission ‘0’: Automatic Retransmission of disturbed messages enabled. ‘1’: Automatic Retransmission disabled.
- Page 426 CAN modules UM0404 Function Last Error Code (Type of the last error to occur on the CAN bus) ’000’: No Error. ’001’: Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. ’010’: Form Error: A fixed format part of a received frame has the wrong format.
- Page 427 UM0404 CAN modules Status interrupts A Status Interrupt is generated by bits BOff and EWarn (Error Interrupt) or by RxOk, TxOk, and LEC (Status Change Interrupt) assumed that the corresponding enable bits in the CAN Control Register are set. A change of bit EPass or a write to RxOk, TxOk, or LEC will never generate a Status Interrupt.
- Page 428 CAN modules UM0404 Function Time segment before the sample point Valid values for TSeg1 are 01h-0Fh (1…15). The actual interpretation by the TSeg1 hardware of this value is such that one more than the value programmed here is used. Time segment after the sample point TSeg2 Valid values for TSeg2 are 0h-7h (0…7).
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Page 429: Message Interface Register Sets
UM0404 CAN modules BRP extension register CAN1BRPER (EF0Ch) XBUS Reset Value: 0000h CAN2BRPER (EE0Ch) XBUS Reset Value: 0000h BRPE Function Baud Rate Prescaler Extension By programming BRPE (0h-Fh) the Baud Rate Prescaler can be extended to values BRPE up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BRP (LSBs) is used. - Page 430 CAN modules UM0404 Table 61. IF1 and IF2 message interface register sets Address IF1 register set Address IF2 register set CAN Base + 0x22 IF1 Data B 1 CAN Base + 0x52 IF2 Data B 1 CAN Base + 0x24 IF1 Data B 2 CAN Base + 0x54 IF2 Data B 2...
- Page 431 UM0404 CAN modules IFx command mask registers The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx Message Buffer Registers are source or target of the data transfer. The bits of IFx Command Mask Register have different functions depending on the transfer direction (Write or Read), defined through WR/RD bit of the register itself.
- Page 432 CAN modules UM0404 Function Access Control Bits Control ’0’: Control Bits unchanged. ’1’: Transfer Control Bits to Message Object. Access Arbitration Bits ’0’: Arbitration bits unchanged. ’1’: Transfer Identifier + Dir + Xtd + MsgVal to Message Object. Access Mask Bits Mask ’0’: Mask bits unchanged.
- Page 433 UM0404 CAN modules IFx Mask Registers CAN1IF1M1 (EF14h) XBUS Reset Value:FFFFh CAN2IF1M1 (EE14h) XBUS Reset Value:FFFFh Msk(15:0) CAN1IF1M2 (EF16h) XBUS Reset Value:FFFFh CAN2IF1M2 (EE16h) XBUS Reset Value:FFFFh MXtd MDir Msk(28:16) CAN1IF2M1 (EF44h) XBUS Reset Value:FFFFh CAN2IF2M1 (EE44h) XBUS Reset Value:FFFFh Msk(15:0) CAN1IF2M2 (EF46h) XBUS...
- Page 434 CAN modules UM0404 IFx arbitration registers CAN1IF1A1 (EF18h) XBUS Reset Value: 0000h CAN2IF1A1 (EE18h) XBUS Reset Value: 0000h ID(15:0) CAN1IF1A2 (EF1Ah) XBUS Reset Value: 0000h CAN2IF1A2 (EE1Ah) XBUS Reset Value: 0000h MsgVal Xtd ID(28:16) CAN1IF2A1 (EF48h) XBUS Reset Value: 0000h CAN2IF2A1 (EE48h) XBUS Reset Value: 0000h...
- Page 435 UM0404 CAN modules Function Extended Identifier ’0’: The standard Identifier (11 bit) will be used for this Message Object. ’1’: The extended Identifier (29 bit) will be used for this Message Object. Message Valid The CPU must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register.
- Page 436 CAN modules UM0404 Function Data Length Code ’0000’: Data Frame has 0 data byte. ’0001’: Data Frame has 1 data byte. ’1000’: Data Frame has 8 data bytes. ’1001’: Data Frame has 8 data bytes. DLC(3:0) ’1111’: Data Frame has 8 data bytes. Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
- Page 437 UM0404 CAN modules Function Message Lost (only valid for Message Objects with direction = receive) ’0’: No message lost since last time this bit was reset by the CPU. MsgLst ’1’: The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
- Page 438 CAN modules UM0404 CAN1IF2DA2 (EF50h) XBUS Reset Value: 0000h CAN2IF2DA2 (EE50h) XBUS Reset Value: 0000h Data(3) Data(2) CAN1IF2DB1 (EF52h) XBUS Reset Value: 0000h CAN2IF2DB1 (EE52h) XBUS Reset Value: 0000h Data(5) Data(4) CAN1IF2DB2 (EF54h) XBUS Reset Value: 0000h CAN2IF2DB2 (EE54h) XBUS Reset Value: 0000h Data(7) Data(6)
- Page 439 UM0404 CAN modules Function Message Valid ’0’: The Message Object is ignored by the Message Handler. ’1’: The Message Object is configured and should be considered by the Message Handler. MsgVal Note: The CPU must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register.
- Page 440 CAN modules UM0404 Function Mask Message Direction ’0’: The message direction bit (Dir) has no effect on the acceptance filtering. ’1’: The message direction bit (Dir) is used for acceptance filtering. The Arbitration Registers ID(28:0), Xtd, and Dir are used to define the identifier and type of outgoing messages and are used (together with the mask registers Msk(28:0), MXtd, and MDir) for acceptance filtering of incoming messages.
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Page 441: Message Handler Registers
UM0404 CAN modules Function Transmit Request TxRqst ’0’: This Message Object is not waiting for transmission. ’1’: The transmission of this Message Object is requested and is not yet done. Data Length Code ’0000’: Data Frame has 0 data byte. ’0001’: Data Frame has 1 data byte. - Page 442 CAN modules UM0404 Function Interrupt identifier (the number here indicates the source of the interrupt) ’0000h’: No interrupt is pending. ’0001h’: Message Object 1 caused the interrupt. ’0020h’: Message Object 32 caused the interrupt. ’0021h’: Unused. IntId(15:0) ’7FFFh’: Unused. ’8000h’: Status Interrupt. ’8001h’: Unused.
- Page 443 UM0404 CAN modules Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission. New data registers CAN1ND1 (EF90h) XBUS Reset Value: 0000h CAN2ND1 (EE90h) XBUS Reset Value: 0000h NewDat(16:1) CAN1ND2 (EF92h) XBUS Reset Value: 0000h CAN2ND2 (EE92h) XBUS...
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Page 444: Can Application
CAN modules UM0404 Function Interrupt Pending Bits (of all Message Objects) IntPnd(32:1) ’0’: This message object is not the source of an interrupt. ’1’: This message object is the source of an interrupt. These registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the CPU can check for which Message Object an interrupt is pending. -
Page 445: Message Handler State Machine
UM0404 CAN modules The configuration of a Message Object is done by programming Mask, Arbitration, Control and Data field of one of the two interface register sets to the desired values. By writing to the corresponding IFx Command Request Register, the IFx Message Buffer Registers are loaded into the addressed Message Object in the Message RAM. -
Page 446: Figure 180. Data Transfer Between Ifx Registers And Message Ram
CAN modules UM0404 Figure 180. Data transfer between IFx registers and message RAM START Write Command Request Register Busy = 1 CAN_WAIT_B = 0 WR/RD = 1 Read Message Object to IFx Read Message Object to IFx Write IFx to Message RAM Busy = 0 CAN_WAIT_B = 1 After the partial write of a Message Object, the Message Buffer Registers that are not... - Page 447 UM0404 CAN modules Acceptance filtering of received messages When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the Rx/Tx Shift Register of the CAN Core, the Message Handler FSM starts the scanning of the Message RAM for a matching valid Message Object.
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Page 448: Configuration Of A Transmit Object
CAN modules UM0404 If more than one transmission request is pending, they are serviced according to the priority of the corresponding Message Object. 21.9.3 Configuration of a transmit object The next diagram shows how a Transmit Object should be initialized. MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst appl appl. -
Page 449: Handling Of Received Messages
UM0404 CAN modules MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst appl appl appl appl The Arbitration Registers (ID(28:0) and Xtd bit) are given by the application. They define the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard Frame”) is used, it is programmed to ID(28:18), while ID(17:0) can then be disregarded. -
Page 450: Reception Of Messages With Fifo Buffers
CAN modules UM0404 implicit priority of the Message Objects, the Message Object with the lowest number will be the first Message Object of the FIFO Buffer. The EoB bit of all Message Objects of a FIFO Buffer except the last have to be programmed to zero. The EoB bits of the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the Block. -
Page 451: Handling Of Interrupts
UM0404 CAN modules Figure 181. CPU handling of a FIFO buffer START Message Interrupt Read Interrupt Pointer case Interrupt Pointer 0x8000h else 0x0000h Status Change Interrupt Handling MessageNum = Interrupt Pointer Write MessageNum to IFx Command Request (Read Message to IFx Registers, Reset NewDat = 0, Reset IntPnd = 0) Read IFx Message Control... -
Page 452: Configuration Of The Bit Timing
CAN modules UM0404 The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is pending, the register will hold the value zero. If the value of the Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set, the interrupt line to the CPU, IRQ_B, is active. -
Page 453: Table 62. Parameters Of The Can Bit Time
UM0404 CAN modules According to the CAN specification, the bit time is divided into four segments (see Figure 182): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer Segment 1 and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 62). -
Page 454: Figure 183. The Propagation Time Segment
CAN modules UM0404 Propagation time segment This part of the bit time is used to compensate physical delay times within the network. These delay times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes. Any CAN node synchronized to the bit stream on the CAN bus will be out of phase with the transmitter of that bit stream, caused by the signal propagation time between the two nodes. - Page 455 UM0404 CAN modules is an example of a minor error in the bit timing configuration (Prop_Seg too short) that causes sporadic bus errors. Some CAN implementations provide an optional 3 Sample Mode: the C-CAN does not. In this mode, the CAN bus input signal passes a digital low-pass filter, using three samples and a majority logic to determine the valid bit value.
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Page 456: Figure 184. Synchronization On "Late" And "Early" Edges
CAN modules UM0404 Apart from noise spikes, most synchronizations are caused by arbitration. All nodes synchronize “hard” on the edge transmitted by the “leading” transceiver that started transmitting first, but due to propagation delay times, they cannot become ideally synchronized. The “leading” transmitter does not necessarily win the arbitration, therefore the receivers have to synchronize themselves to different transmitters that subsequently “take the lead”... -
Page 457: Figure 185. Filtering Of Short Dominant Spikes
UM0404 CAN modules no edge had occurred. As in the previous example, the magnitude of this “early” edge’s phase error is less than SJW, so it is fully compensated. The Phase Buffer Segments are lengthened or shortened temporarily only; at the next bit time, the segments return to their nominal programmed values. - Page 458 CAN modules UM0404 Considering the effect of the system clock discrepancy between two CAN nodes, and supposing no bus errors is detected (due to, for instance, electrical disturbances), bit stuffing guarantees that, also in the worst case condition for the accumulation of phase error (during a normal communication), the maximum time between two re-synchronization edges is 10 bit periods (5 dominant bits followed by 5 recessive bits are always followed by a dominant bit).
- Page 459 UM0404 CAN modules Again calling t the CAN Bit Time, the maximum time t (with correct sampling) between two re-synchronization edges can be expressed as: ⋅ – where t corresponds to the duration of Phase_Seg2 (PB = Phase Buffer). Also in this case, assuming the two CAN nodes with opposite system clock generator tolerance (considering the specified tolerance "df"...
- Page 460 CAN modules UM0404 From two equations above, the new constraints for the CAN system clock tolerance can be translated in new quality requirements for the oscillator: δ ⋅ – < ------------------------------------ - ⋅ ⋅ 2 10 δ ⋅ min t –...
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Page 461: Figure 186. Structure Of The Can Core's Can Protocol Controller
UM0404 CAN modules Figure 186. Structure of the CAN Core’s CAN protocol controller Configuration (BRP) Scaled_Clock (t System Clock Baudrate Control Prescaler Sample_Point Status Sampled_Bit Receive_Data Sync_Mode Timing Bit_to_send Logic Received_Data_Bit Transmit_Data Bus_Off Send_Message Control Shift-Register Next_Data_Bit Received_Message Configuration (TSeg1, TSeg2, SJW) The data in the bit timing registers are the configuration input of the CAN protocol controller. - Page 462 CAN modules UM0404 be defined for expandible CAN bus systems. The resulting time for Prop_Seg is converted into time quanta (rounded up to the nearest integer multiple of t The Sync_Seg is 1 t long (fixed), leaving (bit time – Prop_Seg – 1) t for the two Phase Buffer Segments.
- Page 463 UM0404 CAN modules min t μs ---------------------------------------------- - Tolerance for CAN clock 0.39 % -------------------------------------------------- - ⋅ ⋅ ⋅ ⋅ μs μs – – 13 1 δ (13 x t = 13 x 10 x t = 130 ns = Data from PLL jitter characteristics ⋅...
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Page 464: Real Time Clock
Real time clock UM0404 Real time clock The Real Time Clock is an independent timer, which clock is directly derived from the oscillator clock (either the main on-chip oscillator or the 32 kHz on-chip oscillator), so that it can be maintained running even in Idle or Power Down mode (if enabled to) or again in Stand-by mode. -
Page 465: Figure 187. Sfrs Associated With The Rtc
UM0404 Real time clock Figure 187. SFRs associated with the RTC Interrupt Control 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - Y Y Y Y - - - - - - - Y Y Y Y Y Y Y Y EXISEL E... -
Page 466: Rtc Registers
Real time clock UM0404 Figure 189. RTC block diagram RTCAI RTCSI 32 kHz Oscillator OSC32_STOP Main Clock Oscillator OSC_STOP RTCCON Alarm IT Basic Clock IT Programmable Alarm register Programmable Prescaler register RTCAH RTCAL RTCPH RTCPL Reload RTCH RTCL RTCDH RTCDL 32 bits Counter programmable 20 bits divider 22.1... -
Page 467: Rtcph & Rtcpl: Rtc Prescaler Registers
UM0404 Real time clock Function RTC Second Interrupt Request flag RTCSIR ‘0’: the bit was reset less than one basic clock tick ago. ‘1’: the interrupt was triggered. RTC Second interrupt Enable RTCSEN ‘0’: RTCSI is disabled. ‘1’: RTCSI is enabled, it is generated every basic clock tick. RTC Alarm Interrupt Request flag (when the alarm is triggered) RTCAIR ‘0’: the bit was reset less than a n basic clock tick ago. -
Page 468: Rtcdh & Rtcdl: Rtc Divider Counters
Real time clock UM0404 RTCPH (ED08h) XBUS Reset Value: - - - xh RTCPH Figure 190. Prescaler register 15 14 13 12 11 10 9 RTCPL RTCPH 19 18 17 16 15 14 13 12 11 10 9 20 bit word counter The value stored into RTCPH, RTCPL is called RTCP (coded on 20-bit). -
Page 469: Rtch & Rtcl: Rtc Programmable Counter Registers
UM0404 Real time clock Figure 191. Divider counters 15 14 13 12 11 10 9 RTCDL RTCDH 19 18 17 16 15 14 13 12 11 10 9 20 bit word internal value of the Prescaler divider Bit 15 to bit 4 of RTCPH and RTCDH are not used. When reading, the return value of those bit will be zeros. -
Page 470: Programming The Rtc
Real time clock UM0404 RTCAL (ED12h) XBUS Reset Value: xxxxh RTCAL RTCAH (ED14h) XBUS Reset Value: xxxxh RTCAH Note: These registers are not reset. 22.2 Programming the RTC RTC interrupt request signals are connected to Port2, pin 10 (RTCSI) and pin 11 (RTCAI). An alternate function of Port2 is to generate fast interrupts firq[7:0]. - Page 471 UM0404 Real time clock Function External Interrupt x Source Selection (x 7...0) ‘00’: Input from associated Port2 pin. EXIxSS ‘01’: Input from “alternate source”. ‘10’: Input from Port2 pin ORed with “alternate source”. ‘11’: Input from Port2 pin ANDed with “alternate source”. Note: Recommended configurations.
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Page 472: System Reset
System reset UM0404 System reset System reset initializes the device in a predefined state. There are many ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 63. The reset history is flagged inside WDTCON register (see also Section 14: Watchdog timer on page 297 for additional details). - Page 473 UM0404 System reset internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins. Note: If an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended.
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Page 474: Figure 192. Asynchronous Power-On Reset (Ea = 1)
System reset UM0404 Figure 192 Figure 193 show Asynchronous Power-On timing diagrams, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded Flash module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages. -
Page 475: Figure 193. Asynchronous Power-On Reset (Ea = 0)
UM0404 System reset Figure 193. Asynchronous power-on RESET (EA = 0) ≥ 1.2 ms (for resonator oscillation + PLL stabilization) ≥ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ 1 ms (for on-chip VREG stabilization) 3..8 TCL XTAL1 RSTIN ≥... -
Page 476: Figure 194. Asynchronous Hardware Reset (Ea = 1)
System reset UM0404 Figure 194. Asynchronous hardware RESET (EA = 1) ≤ 2 TCL ≥ 50 ns ≤ 500 ns RSTIN ≥ 50 ns ≤ 500 ns RSTF 3..4 TCL (After Filter) transparent P0[15:13] not transparent not t. not t. not transparent transparent P0[12:2]... -
Page 477: Synchronous Reset (Warm Reset)
UM0404 System reset Figure 195. Asynchronous hardware RESET (EA = 0) 3..8 TCL ≥ 50 ns ≤ 500 ns RSTIN ≥ 50 ns ≤ 500 ns RSTF 3..4 TCL (After Filter) transparent P0[15:13] not transparent not t. not transparent transparent P0[12:2] not t. - Page 478 System reset UM0404 aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software. Note that this bit is always cleared on Power-On or after a reset sequence. Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts.
- Page 479 UM0404 System reset Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (around 2.5V), the reset event becomes immediately asynchronous.
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Page 480: Figure 196. Synchronous Short / Long Hardware Reset (Ea = 1)
System reset UM0404 Figure 196. Synchronous short / long hardware RESET (EA = 1) ≤4 TCL ≤12 TCL < 1032 TCL RSTIN ≥ 50 ns ≥ 50 ns ≥ 50 ns ≤ 2 TCL ≤ 500 ns ≤ 500 ns ≤... -
Page 481: Figure 197. Synchronous Short / Long Hardware Reset (Ea = 0)
UM0404 System reset Figure 197. Synchronous short / long hardware RESET (EA = 0) ≤4 TCL ≤12 TCL < 1032 TCL RSTIN ≥ 50 ns ≥ 50 ns ≥ 50 ns ≤ 500 ns ≤ 500 ns ≤ 500 ns RSTF (After Filter) P0[15:13]... -
Page 482: Figure 198. Synchronous Long Hardware Reset (Ea = 1)
System reset UM0404 Figure 198. Synchronous long hardware RESET (EA = 1) ≤4 TCL ≤12 TCL 1024+8 TCL RSTIN ≥ 50 ns ≥ 50 ns ≥ 50 ns ≤ 2 TCL ≤ 500 ns ≤ 500 ns ≤ 500 ns RSTF (After Filter) 3..4 TCL... -
Page 483: Software Reset
UM0404 System reset Figure 199. Synchronous long hardware RESET (EA = 0) 4 TCL 12 TCL 1024+8 TCL RSTIN ≥ 50 ns ≥ 50 ns ≥ 50 ns ≤ 500 ns ≤ 500 ns ≤ 500 ns RSTF (After Filter) 3..4 TCL P0[15:13] not transparent... -
Page 484: Watchdog Timer Reset
System reset UM0404 A Software reset is always taken as synchronous: there is no influence on Software Reset behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. -
Page 485: Figure 200. Sw / Wdt Unidirectional Reset (Ea = 1)
UM0404 System reset Figure 200. SW / WDT unidirectional RESET (EA = 1) RSTIN ≤ 2 TCL P0[15:13] not transparent not t. transparent P0[12:8] P0[7:2] not transparent P0[1:0] not t. not transparent 7 TCL IBUS-CS (Internal) ≤ 1 ms FLARST 1024 TCL RSTOUT DocID13284 Rev 2... -
Page 486: Bidirectional Reset
System reset UM0404 Figure 201. SW / WDT unidirectional RESET (EA = 0) RSTIN not transparent P0[15:13] transparent not t. P0[12:8] not transparent P0[7:2] P0[1:0] not t. not transparent 8 TCL 1024 TCL RSTOUT 23.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). - Page 487 UM0404 System reset Software or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs.
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Page 488: Figure 202. Sw / Wdt Bidirectional Reset(Ea = 1)
System reset UM0404 Figure 202. SW / WDT bidirectional RESET(EA = 1) RSTIN ≥ ≥ 50 ns 50 ns ≤ ≤ 500 ns 500 ns RSTF (After Filter) P0[15:13] not transparent P0[12:8] transparent not t. P0[7:2] not transparent P0[1:0] not t. not transparent ≤... -
Page 489: Figure 203. Sw / Wdt Bidirectional Reset (Ea = 0)
UM0404 System reset Figure 203. SW / WDT bidirectional RESET (EA = 0) RSTIN ≥ ≥ 50 ns 50 ns ≤ ≤ 500 ns 500 ns RSTF (After Filter) P0[15:13] not transparent not t. P0[12:8] transparent P0[7:2] not transparent P0[1:0] not t. -
Page 490: Reset Circuitry
System reset UM0404 Figure 204. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET RSTIN ≥ ≥ 50 ns 50 ns ≤ ≤ 500 ns 500 ns RSTF (After Filter) P0[15:13] not transparent P0[12:8] transparent not t. P0[7:2] not transparent P0[1:0]... -
Page 491: Figure 205. Minimum External Reset Circuitry
UM0404 System reset C1 that produces a sufficient discharge time to permit the internal or external oscillator and / or internal PLL and the on-chip voltage regulator to stabilize. To ensure correct Power-On reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during Power-On. -
Page 492: Reset Application Examples
System reset UM0404 Figure 206. System reset circuit RSTOUT External Hardware RSTIN External o.d. Reset Source Open Drain Inverter ST10F276 23.8 Reset application examples Next two timing diagrams (Figure 207 Figure 208) provides additional examples of bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to Figure 206 for the... -
Page 493: Figure 207. Example Of Software Or Watchdog Bidirectional Reset (Ea = 1)
UM0404 System reset Figure 207. Example of software or watchdog bidirectional reset (EA = 1) DocID13284 Rev 2 493/564... -
Page 494: Figure 208. Example Of Software Or Watchdog Bidirectional Reset (Ea = 0)
System reset UM0404 Figure 208. Example of software or watchdog bidirectional reset (EA = 0) 494/564 DocID13284 Rev 2... -
Page 495: Reset Summary
UM0404 System reset 23.9 Reset summary A summary of the different reset events is reported in the table below. Table 64. Reset events summary RSTIN WDTCON flags Event 1 ms (VREG) 1.2 ms (Reson. + PLL) Asynch. 10.2 ms (Crystal + PLL) Power-on reset Asynch. -
Page 496: System Start-Up Configuration
System reset UM0404 Table 64. Reset events summary (continued) RSTIN WDTCON flags Event Synch. Not activated Synch. Not activated Software reset Synch. Not activated Synch. Activated by internal logic for 1024 TCL Synch. Not activated Synch. Not activated Watchdog reset Synch. -
Page 497: Table 65. Port0 Latched Configuration For The Different Reset Events
UM0404 System reset Table 65. PORT0 latched configuration for the different reset events PORT0 X : Pin is sampled - : Pin is not sampled Sample event Software Reset Watchdog Reset Synchronous Short Hardware Reset Synchronous Long Hardware Reset Asynchronous Hardware Reset Asynchronous Power-On Reset Figure 209. - Page 498 System reset UM0404 RP0H (F108h / 84h) Reset Value: - - xxh CLKCFG SALSEL CSSEL Function Write Configuration Control ‘0’: Pins WR acts as WRL, pin BHE acts as WRH ‘1’: Pins WR and BHE retain their normal function Chip Select Line Selection (Number of active CS outputs) 0 0: 3 CS lines: CS2...CS0 CSSEL 0 1: 2 CS lines: CS1...CS0...
- Page 499 UM0404 System reset The following describes the different selections that are offered for reset configuration. The default modes refer to pins at high level, without external pull-down devices connected. Emulation mode: P0L.0 When low during reset, pin P0L.0 (EMU) selects the Emulation Mode. This mode allows the access to integrated XBUS peripherals via the external bus interface pins in application specific version of the ST10F276.
- Page 500 System reset UM0404 ST10F276 even for the first code fetch after reset. The two bits are copied into bit-field BTYP of register BUSCON0. P0L.7 controls the data bus width, while P0L.6 controls the address output (multiplexed or de-multiplexed). This bit-field may be changed via software after reset, if required.
- Page 501 UM0404 System reset Note: The selected number of CS signals cannot be changed via software after reset. Segment address lines: P0H.3 - P0H.4 Pins P0H.4 and P0H.3 (SALSEL) define the number of active segment address lines during reset. This determines which pins of Port4 are used as address line or as I/O line. The two bits are latched in register RP0H.
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Page 502: Power Reduction Modes
Power reduction modes UM0404 Power reduction modes Several different power reduction modes with different levels of power reduction have been implemented in the ST10F276, which may be entered under software and/or hardware control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. -
Page 503: Idle Mode
UM0404 Power reduction modes Note: If the on-chip low-power oscillator is not in use, the Real Time Clock module can only be driven by the main oscillator: in this case it is not possible to turn off the main power supply ) of the device, since the main oscillator circuitry would stop working. -
Page 504: Power Down Mode
Power reduction modes UM0404 For a request which was programmed for PEC service, a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and if the interrupt system is globally enabled. After the PEC data transfer has been completed the CPU remains in Idle mode. - Page 505 UM0404 Power reduction modes Note: Leaving the main voltage regulator active during Power Down may lead to unexpected behavior (ex: CPU wake-up) and power consumption higher than what specified. XMISC (EB46h) XBUS Reset Value: 0000h VREG – – Function Port1L ADC Channels Enable ADCMUX ‘0’: Analog inputs on port P5.y can be converted (default configuration) ‘1’: Analog inputs on port P1.z can be converted.
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Page 506: Protected Power Down Mode
Power reduction modes UM0404 Function Power Down Mode Configuration Control ‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. To exit Power Down Mode, an external reset must be provided by asserting the RSTIN pin. PWDCFG ‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled Fast External Interrupt (EXxIN) pins are in their inactive level. -
Page 507: Figure 211. Rpd Pin: External Circuit To Exit Power Down
UM0404 Power reduction modes Function External Interrupt x Edge Selection Field (x 7...0) 0 0: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. 0 1: Interrupt on positive edge (rising) EXIxES Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’... -
Page 508: Figure 212. Simplified Power Down Exit Circuitry
Power reduction modes UM0404 Figure 212). The discharging of the external capacitor provides a delay that allows the oscillator and PLL circuits to stabilize before the internal CPU and Peripheral clocks are enabled. When the voltage on RPD pin drops below the threshold voltage (about 2.5 V), the Schmitt Trigger clears Q2 flip-flop, thus enabling the CPU and Peripheral clocks, and the device resumes code execution. -
Page 509: Stand-By Mode
UM0404 Power reduction modes Figure 213. Power down exit sequence using an external interrupt (PLL x 2) real time clock and power down mode XTAL1 CPU clk Power Down Signal (Internal) External Interrupt ~ 2.5 V ExitPwrd (Internal) Delay for oscillator / PLL stabilization If the Real Time Clock is running (RTOFF bit of RTCCON register cleared), when PWRDN instruction is executed, the oscillator circuit which is providing the reference to the counter is... -
Page 510: Entering Stand-By Mode
Power reduction modes UM0404 interface is frozen in order to avoid any kind of data corruption. It is then possible to turn off the main V provided that V is on. STBY A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that should remain active: the portion of XRAM (16 Kbytes), the RTC counters and 32 kHz on-chip oscillator amplifier. -
Page 511: Exiting Stand-By Mode
UM0404 Power reduction modes from ST10F276 Core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V lower than V ): the bus status could contain a valid address 18SB for the RAM and an unwanted data corruption could occur. -
Page 512: Table 67. Output Pin State During Idle And Power Down Modes
Power reduction modes UM0404 (WR), or to a defined state which is based on the last bus access (BHE). Port pins which are used as external address/data bus hold the address/data which was output during the last external memory access before entry into Idle mode under the following conditions: P0H outputs the high byte of the last address if a multiplexed bus mode with 8-bit data bus is used, otherwise P0H is floating. - Page 513 UM0404 Power reduction modes Note: High if EINIT was executed before entering Idle or Power Down mode, Low otherwise. For multiplexed buses with 8-bit data bus. For de-multiplexed buses. The CS signal that corresponds to the last address remains active (low), all other enabled CS signals remain inactive (high).
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Page 514: Programmable Output Clock Divider
Programmable output clock divider UM0404 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. Real time clock and power down modeXBUS Reset Value: - - 00h Function Clock Divider setting... -
Page 515: Register Set
UM0404 Register set Register set This section summarizes all registers implemented in the ST10F276, and explains the description format used in the sections describing the function and layout of the SFRs. For easy reference the registers (except for GPRs) are ordered in two ways: •... -
Page 516: General Purpose Registers (Gprs)
Register set UM0404 26.2 General purpose registers (GPRs) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the IRAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can only reside within the IRAM. All GPRs are bit-addressable. Table 68. -
Page 517: Special Function Registers Ordered By Name
UM0404 Register set Table 69. General purpose registers (GPRs) bit wise addressing (continued) Physical 8-bit Reset Name Description address address value (CP) + 7 CPU General Purpose (byte) Register RH3 (CP) + 8 CPU General Purpose (byte) Register RL4 (CP) + 9 CPU General Purpose (byte) Register RH4 (CP) + 10 CPU General Purpose (byte) Register RL5... - Page 518 Register set UM0404 Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value FE80h CAPCOM Register 0 0000h CC0IC FF78h CAPCOM Register 0 Interrupt Control Register - - 00h FE82h CAPCOM Register 1 0000h CC1IC FF7Ah...
- Page 519 UM0404 Register set Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value CC17 FE62h CAPCOM Register 17 0000h CC17IC F162h CAPCOM Register 17 Interrupt Control Register - - 00h CC18 FE64h CAPCOM Register 18 0000h CC18IC F164h...
- Page 520 Register set UM0404 Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value CCM4 FF22h CAPCOM Mode Control Register 4 0000h CCM5 FF24h CAPCOM Mode Control Register 5 0000h CCM6 FF26h CAPCOM Mode Control Register 6 0000h CCM7 FF28h...
- Page 521 UM0404 Register set Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value FE0Ch CPU Multiply Divide Register – High Word 0000h FE0Eh CPU Multiply Divide Register – Low Word 0000h FFDAh MAC Unit Repeat Word 0000h FFDEh MAC Unit Status Word...
- Page 522 Register set UM0404 Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value F03Ch PWM Module Period Register 2 0000h F03Eh PWM Module Period Register 3 0000h FF10h CPU Program Status Word 0000h F030h PWM Module Up/Down Counter 0 0000h...
- Page 523 UM0404 Register set Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value SSCTIC FF72h SSC Transmit Interrupt Control Register - - 00h STKOV FE14h CPU Stack Overflow Pointer Register FA00h STKUN FE16h CPU Stack Underflow Pointer Register FC00h SYSCON...
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Page 524: Special Function Registers Ordered By Address
Register set UM0404 Table 70. Special function registers ordered by name (continued) Physical 8-bit Reset Name Description address address value FEAEh Watchdog Timer Register (read only) 0000h WDTCON b FFAEh Watchdog Timer Control Register 00xxh XADRS3 F01Ch XPER Address Select Register 3 800Bh XP0IC F186h... - Page 525 UM0404 Register set Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value F036h E PWM Module Up/Down Counter 3 0000h F038h E PWM Module Period Register 0 0000h F03Ah E PWM Module Period Register 1 0000h F03Ch E PWM Module Period Register 2...
- Page 526 Register set UM0404 Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value CC28IC b F178h E CAPCOM Register 28 Interrupt Control Register - - 00h T7IC F17Ah E CAPCOM Timer 7 Interrupt Control Register - - 00h T8IC F17Ch E...
- Page 527 UM0404 Register set Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value ADDRSEL2 FE1Ah Address Select Register 2 0000h ADDRSEL3 FE1Ch Address Select Register 3 0000h ADDRSEL4 FE1Eh Address Select Register 4 0000h FE30h PWM Module Pulse Width Register 0...
- Page 528 Register set UM0404 Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value CC31 FE7Eh CAPCOM Register 31 0000h FE80h CAPCOM Register 0 0000h FE82h CAPCOM Register 1 0000h FE84h CAPCOM Register 2 0000h FE86h CAPCOM Register 3...
- Page 529 UM0404 Register set Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value IDX0 FF08h MAC Unit Address Pointer 0 0000h IDX1 FF0Ah MAC Unit Address Pointer 1 0000h BUSCON0 b FF0Ch Bus Configuration Register 0 0xx0h FF0Eh CPU Multiply Divide Control Register...
- Page 530 Register set UM0404 Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value CRIC FF6Ah GPT2 CAPREL Interrupt Control Register - - 00h S0TIC FF6Ch Serial Channel 0 Transmit Interrupt Control Register - - 00h S0RIC FF6Eh Serial Channel 0 Receive Interrupt Control Register...
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Page 531: X-Registers Ordered By Name
UM0404 Register set Table 71. Special function registers ordered by address (continued) Physical 8-bit Reset Name Description address address value FFC0h Port2 Register 0000h DP2b FFC2h Port2 Direction Control Register 0000h FFC4h Port3 Register 0000h DP3b FFC6h Port3 Direction Control Register 0000h FFC8h Port4 Register (8-bit) - Page 532 Register set UM0404 Table 72. X-Registers ordered by name (continued) Reset Name Physical address Description value CAN1IF1DB1 EF22h CAN1: IF1 Data B 1 0000h CAN1IF1DB2 EF24h CAN1: IF1 Data B 2 0000h CAN1IF1M1 EF14h CAN1: IF1 Mask 1 FFFFh CAN1IF1M2 EF16h CAN1: IF1 Mask 2 FFFFh...
- Page 533 UM0404 Register set Table 72. X-Registers ordered by name (continued) Reset Name Physical address Description value CAN2IF1CR EE10h CAN2: IF1 Command Request 0001h CAN2IF1DA1 EE1Eh CAN2: IF1 Data A 1 0000h CAN2IF1DA2 EE20h CAN2: IF1 Data A 2 0000h CAN2IF1DB1 EE22h CAN2: IF1 Data B 1 0000h...
- Page 534 Register set UM0404 Table 72. X-Registers ordered by name (continued) Reset Name Physical address Description value I2COAR1 EA08h I2C Own Address Register 1 0000h I2COAR2 EA0Ah I2C Own Address Register 1 0000h I2CSR1 EA02h I2C Status Register 1 0000h I2CSR2 EA04h I2C Status Register 2 0000h...
- Page 535 UM0404 Register set Table 72. X-Registers ordered by name (continued) Reset Name Physical address Description value Extended Port Input Threshold Control XPICON EB26h - - 00h Register XPOLAR EC04h XPWM Module Channel Polarity Register 0000h XPP0 EC20h XPWM Module Period Register 0 0000h XPP1 EC22h...
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Page 536: X-Registers Ordered By Address
Register set UM0404 Table 72. X-Registers ordered by name (continued) Reset Name Physical address Description value XSSCCONCLR E804h XSSC Clear Control Register (write only) 0000h XSSCCONSET E802h XSSC Set Control Register (write only) 0000h XSSCPORT E880h XSSC Port Control Register 0000h XSSCRB E808h... - Page 537 UM0404 Register set Table 73. X-Registers ordered by address (continued) Reset Name Physical address Description value I2COAR1 EA08h I2C Own Address Register 1 0000h I2COAR2 EA0Ah I2C Own Address Register 1 0000h I2CDR EA0Ch I2C Data Register 0000h I2CCCR2 EA0Eh I2C Clock Control Register 2 0000h XCLKOUTDIV...
- Page 538 Register set UM0404 Table 73. X-Registers ordered by address (continued) Reset Name Physical address Description value XPWM Module Set Control Register 0 XPWMCON1SET EC0Ah 0000h (write only) XPWM Module Clear Control Reg. 0 (write XPWMCON1CLR EC0Ch 0000h only) XPT0 EC10h XPWM Module Up/Down Counter 0 0000h XPT1...
- Page 539 UM0404 Register set Table 73. X-Registers ordered by address (continued) Reset Name Physical address Description value CAN2IF1M1 EE14h CAN2: IF1 Mask 1 FFFFh CAN2IF1M2 EE16h CAN2: IF1 Mask 2 FFFFh CAN2IF1A1 EE18h CAN2: IF1 Arbitration 1 0000h CAN2IF1A2 EE1Ah CAN2: IF1 Arbitration 2 0000h CAN2IF1MC EE1Ch...
- Page 540 Register set UM0404 Table 73. X-Registers ordered by address (continued) Reset Name Physical address Description value CAN1BRPER EF0Ch CAN1: BRP Extension Register 0000h CAN1IF1CR EF10h CAN1: IF1 Command Request 0001h CAN1IF1CM EF12h CAN1: IF1 Command Mask 0000h CAN1IF1M1 EF14h CAN1: IF1 Mask 1 FFFFh CAN1IF1M2 EF16h...
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Page 541: Flash Registers Ordered By Name
UM0404 Register set 26.7 Flash registers ordered by name The following table lists all Flash Control Registers which are implemented in the ST10F276 ordered by their name. Note that as they are physically mapped on the X-Bus, these registers are not bit-addressable. Table 74. -
Page 542: Special Notes
Register set UM0404 Table 75. Flash registers ordered by address (continued) Reset Name Physical address Description value FCR1H 0x000E 0006 Flash Control Register 1 - High 0000h FDR0L 0x000E 0008 Flash Data Register 0 - Low FFFFh FDR0H 0x000E 000A Flash Data Register 0 - High FFFFh FDR1L... -
Page 543: Identification Registers
UM0404 Register set Writing byte to SFRs All special function registers may be accessed word wise or byte wise (some of them even bit wise). Reading byte from word SFRs is a non-critical operation. However, when writing byte to word SFRs the complementary byte of the respective SFR is cleared with the write operation. - Page 544 Register set UM0404 Function Internal Memory Size MEMSIZE Internal Memory size is 4 x (MEMSIZE) (in Kbyte) 0D0h for ST10F276 (832 Kbytes) Internal Memory Type ‘0h’: ROM-Less ‘1h’: (M) ROM memory MEMTYP ‘2h’: (S) Standard Flash memory ‘3h’: (H) High Performance Flash memory (ST10F276x) ‘4h...Fh’: reserved IDPROG (F078h / 3Ch) ESFR...
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Page 545: System Programming
UM0404 System programming System programming Constructs for modularity, loops, and context switching have been built into the ST10F276 instruction set. Many commonly used instruction sequences have been simplified. The following programming features are available to the programmer. Instructions provided as subsets of instructions In many cases, instructions found in other microcontrollers are provided as subsets of more powerful instructions in the ST10F276. - Page 546 System programming UM0404 Multiplication or division is simply performed by specifying the correct (signed or unsigned) version of the multiply or divide instruction. The result is then stored in register MD. The overflow flag (V) is set if the result from a multiply or divide instruction is greater than 16-bit.
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Page 547: Stack Operations
UM0404 System programming Whenever a multiply or divide instruction is interrupted while in progress, the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set. When the interrupt routine is exited with the RETI instruction, this bit is implicitly tested before the old PSW is popped from the stack. -
Page 548: Table 76. Stack Size Selection
System programming UM0404 The contents of the stack pointer are compared to the contents of the underflow register, whenever the SP is INCREMENTED either by a RET, POP or ADD instruction. An underflow trap will be entered, when the SP value is greater than the value in the stack underflow register. -
Page 549: Figure 214. Physical Stack Address Generation
UM0404 System programming Table 76. Stack size selection (continued) Stack size IRAM addresses (words) Significant bit of (STKSZ) (words) of physical stack stack pointer SP 1 0 1 b Reserved. Do not use this combination. 1 1 0 b Reserved. Do not use this combination. 1 1 1 b 1024 00’FDFEh...00’F600h (Note: No circular stack) - Page 550 System programming UM0404 this circular stack mechanism only requires to move that portion of stack data which is really to be re-used (the upper part of the defined stack area) instead of the whole stack area. Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled, as the stack pointer automatically wraps around to the beginning of the freed part of the stack area.
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Page 551: Register Banking
UM0404 System programming User stacks User stacks provide the ability to create task specific data stacks and to off-load data from the system stack. The user may push both byte and words onto a user stack, but is responsible for using the appropriate instructions when popping data from the specific user stack. - Page 552 System programming UM0404 a mechanism of accessing data referenced by data pointers, which are passed to the subroutine. In addition, two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead. The PCALL (push and call) instruction first pushes the 'reg' operand and the IP contents onto the system stack and then passes control to the subroutine specified by the 'caddr' operand.
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Page 553: Figure 215. Local Registers
UM0404 System programming Figure 215. Local registers Old Stack Area Old SP Newly Allocated Register Bank New CP New SP Old CP Contents New Stack Area Software to provide the local register bank for the example in Figure 215 is very compact: After entering the subroutine: SP, #10D ;... -
Page 554: Peripheral Control And Interface
System programming UM0404 27.5 Peripheral control and interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory, or by explicitly addressing the SFRs associated with the specific peripherals. After resetting the ST10F276 all peripherals (except the watchdog timer) are disabled and initialized to default values. -
Page 555: Inseparable Instruction Sequences
UM0404 System programming 27.8 Inseparable instruction sequences The instructions of the ST10F276 are very efficient (most instructions execute in one instruction cycle) and even the multiplication and division are interruptible in order to minimize the response latency to interrupt requests (internal and external). In many microcontroller applications this is vital. -
Page 556: Handling The Internal Flash
System programming UM0404 The EXTS (extend segment) instruction allows switching to a 64 Kbyte segment oriented data access scheme for 1...4 instructions without having to change the current DPPs. In this case all 16 bits of the operand address are used as segment offset, with the segment taken from the EXTS instruction. - Page 557 UM0404 System programming When the EA pin is high during reset (default value), the internal Flash is globally enabled and the first 32 Kbytes are mapped in segment ‘0’. The first instructions are fetched from the internal Flash from locations 00’0000h. When the EA pin is low during reset (ROMEN = 0), the internal Flash is disabled and external memory is used for startup control.
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Page 558: Pits, Traps And Mines
System programming UM0404 If the internal Flash only contains the start-up code and/or test software, the system may be booted from internal Flash, which may then be disabled, after the software has switched to executing from external memory, in order to free the address space occupied by the internal Flash area, which is now unnecessary. - Page 559 UM0404 Abbreviations Appendix A Abbreviations The following abbreviations and acronyms are used in this user manual: Alternate Boot Mode Analog Digital Converter Address Latch Enable Arithmetic and Logic Unit Asynchronous/synchronous Serial Controller Baud Rate Generator Controller Area Network (License Bosch CAPCOM CAPture and COMpare unit CISC...
- Page 560 Document references UM0404 Appendix B Document references 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM (ST10F276E, DocID12303) 16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM (ST10F276Z5, DocID12448) 560/564 DocID13284 Rev 2...
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Page 561: Table 77. Document Revision History
Revision history Revision history Table 77. Document revision history Date Revision Changes It is the first official release of the document, just for ST internal 21-Feb-2003 review only. 1-Sep-2003 Many modifications according to internal review procedure. 1-Oct-2003 Minor modifications according to internal review procedure. - Page 562 Revision history UM0404 Table 77. Document revision history (continued) Date Revision Changes Figure 4 on page 41 Figure 6 on page 45 updated: B0F6 into B0F7. XPER-SHARE Mode limits added in paragraph Section 2.4.1: XRAM access via external masters on page Bit XPER-SHARE in SYSCON: description updated.
- Page 563 UM0404 Revision history Table 77. Document revision history (continued) Date Revision Changes Sections 10 to 16 re-ordered as in the original version (bad order in rev. 1.5 only). Section 7: Dedicated pins on page 179: added V and V AREF AGND dedicated pins in the table.
- Page 564 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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