ST ST10F276Z5 Manuals

Manuals and User Guides for ST ST10F276Z5. We have 1 ST ST10F276Z5 manual available for free PDF download: User Manual

ST ST10F276Z5 User Manual (564 pages)

High performance 16-bit microcontrollers

Brand: ST | Category: Microcontrollers | Size: 22 MB

Table of Contents
2
Architectural Overview

22
- Basic CPU Concepts and Optimization
  22
- On-Chip System Resources
  27
- Clock Generator
  30
  - Figure 3. Clock Block Diagram
    30
  - Direct Drive
    31
  - PLL Operation
    31
  - Prescaler Operation
    31
  - Oscillator Watchdog (OWD)
    32
- On-Chip Peripheral Blocks
  32
  - Peripheral Interfaces
    33
  - Peripheral Timing
    33
  - Programming Hints
    33
  - Parallel Ports
    34
  - Serial Channels
    34
  - General Purpose Timer (GPT) Unit
    35
  - Watchdog Timer
    36
  - Capture / Compare (CAPCOM) Units
    36
  - Pulse Width Modulation Unit
    37
  - A/D Converter
    37
  - CAN Module
    38
  - I2C Serial Interface
    38
- Real Time Clock
  38
- Protected Bits
  39
- Table 1. Protected Bit
  39
Memory Organization

40
The Central Processing Unit (CPU)

52
Multiply-Accumulate Unit (MAC)

82
Interrupt and Trap Functions

96
- Interrupt System Structure
  96
- Operation of the PEC Channels
  104
- Table 17. PEC Control Register Addresses
  104
- Prioritizing Interrupt & PEC Service Requests
  106
- Saving the Status During Interrupt Service
  108
  - Context Switching
    109
  - Figure 21. Task Status Saved on the System Stack
    109
- Interrupt Response Times
  110
- External Interrupts
  113
  - Table 19. Pins to be Used as External Interrupt Inputs
    114
  - Fast External Interrupts
    115
- X-Peripheral Interrupt
  117
- Table 20. X-Interrupt Detailed Mapping
  118
- Figure 24. X-Interrupt Basic Structure
  118
- Trap Functions
  128
  - Table 21. Trap Priorities
    128
  - Hardware Traps
    129
  - Software Traps
    129
  - External NMI Trap
    131
  - Stack Overflow Trap
    131
  - MAC Interrupt
    132
  - Protection Fault Trap
    132
  - Stack Underflow Trap
    132
  - Undefined Opcode Trap
    132
  - Illegal External Bus Access Trap
    133
  - Illegal Instruction Access Trap
    133
  - Illegal Word Operand Access Trap
    133
Parallel Ports

134
- Introduction
  134
- Port0
  139
  - Alternate Functions of PORT0
    140
  - Figure 28. PORT0 I/O and Alternate Functions
    141
- Port1
  142
- Port2
  146
- Port3
  150
- Port4
  154
- Port5
  161
- Port6
  164
- Port7
  169
- Port8
  172
Dedicated Pins

179
- Table 29. Summary of Dedicated Pins
  179
- Figure 56. RPD External RC Circuit
  180
The External Bus Interface

181
The General Purpose Timer Units

215
- Timer Block GPT1
  215
- Timer Block GPT2
  232
Asynchronous / Synchronous Serial Interface

246
XBUS Asynchronous / Synchronous Serial Interface

257
High-Speed Synchronous Serial Interface

270
XBUS High-Speed Synchronous Serial Interface

284
Watchdog Timer

297
The Bootstrap Loader

302
- Selection Among User-Code, Standard or Alternate Bootstrap
  302
- Standard Bootstrap Loader
  303
- Standard Bootstrap with UART (RS232 or K-Line)
  309
- Standard Bootstrap with CAN
  313
- Comparing the Old and the New Bootstrap Loader
  319
  - Software Aspects
    319
  - Table 47. Software Topics Summary
    319
  - Hardware Aspects
    320
- Alternate Boot Mode (ABM)
  320
  - Activation
    320
  - Memory Mapping
    320
  - Interrupts
    320
  - Table 48. Hardware Topics Summary
    320
  - ST10 Configuration in Alternate Boot Mode
    321
  - Watchdog
    321
  - Exiting Alternate Boot Mode
    321
  - Alternate Boot User Software
    322
  - User/Alternate Mode Signature Integrity Check
    322
  - Alternate Boot User Software Aspects
    322
  - EMUCON Register
    322
  - Internal Decoding of Test Modes
    323
  - Example
    323
- Selective Boot Mode
  323
- Figure 132. Reset Boot Sequence
  325
The Capture / Compare Units

326
Pulse Width Modulation Module

345
XBUS Pulse Width Modulation Module

357
Analog / Digital Converter

370
I 2 C Interface

392
- Main Features
  392
- General Description
  393
  - Mode Selection
    393
  - Communication Flow
    393
  - Figure 168. I2C Bus Protocol
    393
  - SDA/SCL Line Control
    394
- Functional Description
  395
  - Slave Mode
    395
  - Figure 169. I 2 C Interface Block Diagram
    395
  - Master Mode
    397
  - Figure 170. Transfer Sequencing
    399
- Interrupts
  400
- Table 57. Interrupt Event Summary
  401
- Figure 171. Event Flags and Interrupt Generation
  401
- Register Description
  403
CAN Modules

410
- Memory and Pin Mapping
  410
  - CAN1 Mapping
    410
  - CAN2 Mapping
    410
  - Register Summary
    410
  - Table 58. CAN1 Register Mapping
    411
  - Table 59. CAN2 Register Mapping
    412
- Interrupt
  413
- Configuration Support
  413
- Clock Prescaling
  416
- Figure 174. Connection to Two Different CAN Buses (E.g. for Gateway Application)
  416
- Figure 175. Connection to One CAN Bus with Internal Parallel Mode Enabled
  416
- CAN Module: Functional Overview
  417
- Block Diagram
  418
- Operating Modes
  418
  - Software Initialization
    418
  - Figure 176. Block Diagram of the C-CAN
    418
  - CAN Message Transfer
    419
  - Disabled Automatic Re-Transmission
    419
  - Test Mode
    420
  - Silent Mode
    420
  - Loop Back Mode
    420
  - Figure 177. CAN Core in Silent Mode
    420
  - Loop Back Combined with Silent Mode
    421
  - Figure 178. CAN Core in Loop Back Mode
    421
  - Figure 179. CAN Core in Loop Back Combined with Silent Mode
    421
  - Basic Mode
    422
  - Software Control of Pin Can_Txd
    422
- Programmer's Model
  422
- CAN Application
  444
Real Time Clock

464
- Figure 187. Sfrs Associated with the RTC
  465
- Figure 188. XBUS Registers Associated with the RTC
  465
- RTC Registers
  466
- Programming the RTC
  470
System Reset

472
Power Reduction Modes

502
- Idle Mode
  503
- Table 66. Power Reduction Modes Summary
  503
- Power down Mode
  504
  - Down Mode
    504
    
    Protected Power down Mode
    506
    
    Interruptible Power down Mode
    506
    
    Figure 211. RPD Pin: External Circuit to Exit Power down
    507
    
    Figure 212. Simplified Power down Exit Circuitry
    508
  - Figure 210. Transitions between Idle Mode and Active Mode
    504
  - Stand-By Mode
    509
    
    Entering Stand-By Mode
    510
    
    Exiting Stand-By Mode
    511
    
    Real Time Clock and Stand-By Mode
    511
  - Output Pin Status
    511
  - Table 67. Output Pin State During Idle and Power down Modes
    512
Programmable Output Clock Divider

514
Register Set

515
System Programming

545
- Stack Operations
  547
- Table 76. Stack Size Selection
  548
- Figure 214. Physical Stack Address Generation
  549
- Register Banking
  551
- Procedure Call Entry and Exit
  551
- Figure 215. Local Registers
  553
- Peripheral Control and Interface
  554
- Floating Point Support
  554
- Trap / Interrupt Entry and Exit
  554
- Inseparable Instruction Sequences
  555
- Overriding the DPP Addressing Mechanism
  555
- Handling the Internal Flash
  556
- Pits, Traps and Mines
  558
- Table 77. Document Revision History
  561

ST Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More ST Manuals

ST ST10F276Z5 Manuals

ST ST10F276Z5 User Manual (564 pages)

Table of Contents

Architectural Overview

Memory Organization

The Central Processing Unit (CPU)

Multiply-Accumulate Unit (MAC)

Interrupt and Trap Functions

Parallel Ports

Dedicated Pins

The External Bus Interface

The General Purpose Timer Units

Asynchronous / Synchronous Serial Interface

XBUS Asynchronous / Synchronous Serial Interface

High-Speed Synchronous Serial Interface

XBUS High-Speed Synchronous Serial Interface

Watchdog Timer

The Bootstrap Loader

The Capture / Compare Units

Pulse Width Modulation Module

XBUS Pulse Width Modulation Module

Analog / Digital Converter

I 2 C Interface

CAN Modules

Real Time Clock

System Reset

Power Reduction Modes

Programmable Output Clock Divider

Register Set

System Programming

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