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Appendices
PCI Express Port
Provides BIOS Chipset details for the submenu Platform Controller Hub / PCI Express Configura-
tion / PCI Express Port.
Changeable BIOS PCI Express Port parameters and their factory default values:
PCI Express Port
Topology
ASPM
Gen 3 Eq Phase3 Method
UPTP
DPTP
ACS
URR
FER
NFER
CER
CTO
SEFE
SENFE
SECE
PME SCI
Hot Plug
Advanced Error Reporting
PCIe Speed
Transmitter Half Swing
Detect Timeout
PCH PCIE£ LTR
Snoop Latency Override
Non Snoop Latency Override
Force LTR Override
PCIE£ LTR Lock
Extra options
*1.
CPU specific:
•
For 7
•
For 6
*2.
The default does not change but the PCIE number is port specific.
•
For 7
Port 0: PCIE1. Port 2: PCIE3. Port 3: PCIE4. Port 4: PCIE5. Port 6: PCIE9.
•
For 6
Port 0: PCIE5. Port 1: PCIE6. Port 2: PCIE7. Port 3: PCIE8. Port 4: PCIE9. Port 5: PCIE10. Port 6:
PCIE11. Port 7: PCIE12.
A-42
Item
*2
*2
Detect Non-Compliance Device
Prefetchable Memory
Reserved Memory Alignment
Prefetchable Memory Alignment
th
generation CPUs: Port 0, 4 = Unknown. Port 2, 3, 6 = x1.
th
generation CPUs: Port 0, 1, 2, 5, 6, 7 = Unknown. Port 3, 4 = x1.
th
generation CPUs:
th
generation CPUs:
Enabled
CPU specific
Disabled
Software Search
5
7
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
Auto
Disabled
0
Enabled
Auto
Auto
Disabled
Disabled
Disabled
10
1
1
NY-series Industrial Box PC Hardware User's Manual (W553)
Default / Remark
*1
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