Sony HCD-C5 Service Manual page 69

• IC151 CXD2662R
• (DIGITAL SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER) (BD (MD) BOARD)
Pin No. Pin Name
1 MNT0 (FOK)
2 MNT1 (SHCK)
3 MNT2 (XBUSY)
4 MNT3 (SLOC)
5 SWDT
6 SCLK
7 XLAT
8 SRDT
9 SENS
10 XRST
11 SQSY
12 DQSY
13 RECP
14 XINT
15 TX
16 OSCI
17 OSCO
18 XTSL
19 DIN0
20 DIN1
21 DOUT
22 DATI
23 LRCKI
24 XBCKI
25 ADDT
26 DADT
27 LRCK
28 XBCK
29 FS256
30 DVDD
31 to 34 A03 to A00
35 A10
36 to 40 A04 to A08
41 A11
42 DVSS
43 XOE
44 XCAS
45 A09
46 XRAS
47 XWE
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
I/O
O Focus OK signal output terminal "H" is output when focus is on ("L": NG) Not used (open)
O Track jump detection signal output to the MD mechanism controller (IC1001)
O Busy monitor signal output to the MD mechanism controller (IC1001)
O Spindle servo lock status monitor signal output to the MD mechanism controller (IC1001) (open)
I Writing serial data signal input from the MD mechanism controller (IC1001)
I (S) Serial data transfer clock signal input from the MD mechanism controller (IC1001)
I (S) Serial data latch pulse signal input from the MD mechanism controller (IC1001)
O (3) Reading serial data signal output to the MD mechanism controller (IC1001)
O (3) Internal status (SENSE) output to the MD mechanism controller (IC1001)
I (S) Reset signal input from the MD mechanism controller (IC1001) "L": reset
Subcode Q sync (SCOR) output to the MD mechanism controller (IC1001)
O
"L" is output every 13.3 msec
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism controller
O
(IC1001) "L" is output every 13.3 msec
Laser power selection signal input from the MD mechanism controller (IC1001)
I
"L": playback mode, "H": recording mode
O Interrupt status output to the MD mechanism controller (IC1001)
O Magnetic head on/off signal output to the over write head drive (IC181)
I System clock signal (90.3168 MHz) input terminal
O System clock signal (512Fs=90.3168 MHz) output terminal Not used (open)
Input terminal for the system clock frequency setting
I
"L": 45.1584 MHz, "H": 90.3168 MHz (fixed at "H" in this set)
I Digital audio signal input terminal when recording mode Not used
I Digital audio signal input terminal when recording mode
O Digital audio signal output terminal when playback mode
I Recording data input from the A/D converter (IC1005)
L/R sampling clock signal (44.1 kHz) input from the D/A converter (IC1006), A/D converter
I
(IC1005)
I Bit clock signal (2.8224 MHz) input from the D/A converter (IC1006), A/D converter (IC1005)
I Recording data input terminal Not used (fixed at "L")
O Playback data output terminal Not used (open)
O L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
O Bit clock signal (2.8224 MHz) output terminal Not used (open)
O Clock signal (11.2896 MHz) output terminal Not used (open)
— Power supply terminal (+3.3V) (digital system)
O Address signal output to the D-RAM (IC152)
O Address signal output to the D-RAM (IC152) (open)
O Address signal output to the D-RAM (IC152)
O Address signal output to the external D-RAM Not used (open)
— Ground terminal (digital system)
O Output enable signal output to the D-RAM (IC152) "L" active
O Column address strobe signal output to the D-RAM (IC152) "L" active
O Address signal output to the D-RAM (IC152)
O Row address strobe signal output to the D-RAM (IC152) "L" active
O Write enable signal output to the D-RAM (IC152) "L" active
Description
Almost all, "H" is output
Almost all, "H" is output
HCD-C5
69