Linear Technology Analog Devices LT8301 Datasheet page 14

LT8301
APPLICATIONS INFORMATION
Tables 2 and 3 show some recommended diodes and
Zener diodes.
Table 2. Recommended Zener Diodes
V POWER
ZENER
PART (V) (W)
CMDZ5248B 18 0.25
CMDZ5250B 20 0.25
Table 3. Recommended Diodes
I V
MAX REVERSE
PART (A) (V)
CMHD4448 0.25 100
DFLS1100 1 100
DFLS1150 1 150
The recommended approach for designing an RC snub-
ber is to measure the period of the ringing on the SW
pin when the power switch turns off without the snub-
ber and then add capacitance (starting with 100pF) until
the period of the ringing is 1.5 to 2 times longer. The
change in period will determine the value of the parasitic
capacitance, from which the parasitic inductance can be
determined from the initial period, as well. Once the value
of the SW node capacitance and inductance is known, a
series resistor can be added to the snubber capacitance
to dissipate power and critically dampen the ringing. The
equation for deriving the optimal series resistance using
the observed periods ( t
PERIOD
snubber capacitance (C
SNUBBER
C
SNUBBER
C
=
PAR
t
⎛
PERIOD(SNUBBED)
⎝ ⎜
t
PERIOD
2
t
PERIOD
L
=
PAR
2
C • 4π
PAR
L
PAR
R
=
SNUBBER
C
PAR
14
CASE VENDOR
SOD-323 Central Semiconductor
SOD-323
CASE VENDOR
SOD-123 Central Semiconductor
PowerDI-123 Diodes Inc.
PowerDI-123 Diodes Inc.
and t ) and
PERIOD(SNUBBED)
) is:
2
⎞
− 1
⎠ ⎟
For more information
Note that energy absorbed by the RC snubber will be
converted to heat and will not be delivered to the load.
In high voltage or high current applications, the snubber
may need to be sized for thermal dissipation.
Undervoltage Lockout (UVLO)
A resistive divider from V
ments undervoltage lockout (UVLO). The EN/UVLO pin
falling threshold is set at 1.228V with 14mV hysteresis.
In addition, the EN/UVLO pin sinks 2.5µA when the volt-
age at the pin is below 1.228V. This current provides user
programmable hysteresis based on the value of R1. The
programmable UVLO thresholds are:
1.242V • (R1+ R2)
V
=
IN(UVLO+)
R2
1.228V • (R1+ R2)
V
=
IN(UVLO−)
R2
Figure 7 shows the implementation of external shutdown
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on, and puts the
LT8301 in shutdown with quiescent current less than 2µA.
EN/UVLO
LT8301
GND
8301 F07
Figure 7. Undervoltage Lockout (UVLO)
www.analog.com
to the EN/UVLO pin imple-
IN
+ 2.5µA • R1
V
IN
R1
RUN/STOP
R2
CONTROL
(OPTIONAL)
Rev. A