Scion Instruments 436-GC Service Manual page 87

436-GC/456-GC
Feedback capacitor C22 configures amplifier AR2 as an integrator, so a constant current into the collector
of Q4 causes a rising, linear ramp at the output of AR2 (pin 6).
The noninverting input of comparator AR3 is biased to +3V by R26 and R34. Since the ramp voltage from
AR2 is applied to the inverting input of AR3 through R33, the output of the comparator (pin 7) will switch
from high to low when the ramp voltage reaches 3V. CR5 and CR6 provide hysteresis, ensuring that the
comparator output stays low until the ramp has been reset to zero volts. The output of AR3 is an open-
collector transistor, so R25 is needed to pull the output up to 5V when the transistor turns off.
When the comparator output switches low, Q5 is turned on, discharging C22 and resetting the ramp. R31
keeps Q5 turned on until the ramp voltage has fallen all the way to ground. The bias current flowing into pin
2 of AR2 (typically 150nA) would keep the current-to-frequency converter running at about 500 pulses per
second even if the collector current of Q4 were zero. R30 sources enough current into the amplifier input
node to cancel the input bias current, so that the operating frequency can go below 500Hz in all cases.
Pulser.
Each time the output of comparator AR3 switches from high to low, one-shot U4 generates a positive pulse
at pin 13. R24 and C12 set the pulse width to 640ns. Buffer U1 has its individual sections tied in parallel to
provide the large drive currents needed to charge the gate capacitances of Q2 and Q3. In between pulses,
the outputs of U1 are at ground, and the gate voltage of Q2 is held at -4.5V by R16 and R18. Since Q2 is a
p-channel MOSFET, it is turned on when the gate is negative, and the pulser output at J2 is equal to the
source voltage at pin 1 of Q2. Q3 (an n-channel device) is turned off during this time, since R20 holds its
gate at the same voltage as its source (-50V).
When a pulse from the current-to-frequency converter causes the outputs of U1 to switch to +5V, the gate
voltages of both FETs rise by about 5V. Q2 turns off while Q3 turns on, pulling the pulser output to -50V.
R19 improves the settling time of the output pulse. C7 forces the gate voltage of Q2 to switch rapidly, while
C11 allows the DC voltages at U1and at the gate of Q3 to be different. CR2 clamps the negative
excursions of Q3's gate voltage to the -50V supply, so that the FET continues to be turned on hard even at
high pulse frequencies, where it may be on more than 50% of the time.
DACs.
Detector operation requires the pulser output to have a variable DC offset, which is provided by one half of
a dual DAC (U8). AR5 (pins 1-3), R50, and R51 invert the +10V reference, supplying -10V at U8-4 and U8-
18. AR5 (pins 8-10) converts the output current of the DAC to a voltage, which varies from 0 to +9.96V as
the digital code written to the DAC varies from 0 to 255. To find the voltage at AR6-3, note that R52 is
connected to the inverting input of AR6 (pin 6), which remains at a virtual ground potential. R15 offsets the
voltage at AR6-3 down by about half the output range of the DAC, resulting in a voltage range of -769mV to
+763mV as the DAC setting is varied from 0 to 255. AR6 (pins 1-3) provides a low-impedance output to
drive the pulser, and R17 and C8 keep the high-frequency pulser currents out of the amplifier's output. At
the highest pulse frequencies, the DC current flowing through R17 can cause as much as 100mV of drop,
especially when driving high capacitances at the pulser output.
The other half of dual DAC U8 operates in exactly the same way, generating a voltage between 0 and
+9.96V at AR5-7. In normal operation, analog switch U3 (pins 14 and 15)
is open, and the DAC output voltage appears at the bottom end of R27. (The effect of R49 is negligible in
series with R27, which is 50,000 times larger.)
Electrometer
The other end of R27 is tied to the inverting input of AR1, which must stay at ground (equal to the
noninverting input voltage) for the amplifier to function linearly. This means that a current between 0 and
2nA must flow through R27 into the summing junction at AR1-2. Since the input current of AR1 is only a
few femtoamps (1fA = 1E-15A), and no DC current can flow through the capacitors connected to AR1-2 ,
all of the current supplied by the DAC through R27 must flow out through the ECD input connector. The
puller output is normally connected to an electron capture detector (ECD) cell, which draws a small charge
from the ECD input through J1 with each pulse.
As the composition of the gas in the cell changes, the magnitude of the charge varies, and the circuitry on
this board adjusts the pulse frequency to exactly balance the current set by the DAC with the current from
the cell.
SCION Instruments
436-GC/456-GC Service Manual Revision B February 2019
610 Hardware description
Page: 86