Fid Electronics Circuit Description - Scion Instruments 436-GC Service Manual

436-GC/456-GC

FID Electronics Circuit Description

Power supplies and grounds.
There are four grounds serving the F1D electronics circuitry. Ground 1 is the return for the +5V digital
supply. It is connected directly to Ground 4, the unregulated +24V return, at the card edge connector on
the Mother board. The analog return is Ground 2, which provides a low-noise return for the ±15V and
+5.25V supplies. Ground 3 is the reference for analog signal distribution, which carries almost no DC
current. All of the grounds must be tied together externally for the board to function properly.
Three RC filters remove noise from the analog power supplies. These consist of R24 with C13, R23 with
C12, and R22 with Cll.
Digital circuits.
U7 decodes bus address information to access latch U6 and buffer U5. The latch holds all of the digital
control signals for the board, while the buffer transmits the board identification number and serial data from
EEPROM U8 to the bus. R25 allows the inputs of U5 to be pulled high for test, while remaining low in
normal operation.
The EEPROM is a 1024-bit device which is used to store calibration data. Software has full control over the
serial interface, consisting of the chip select, shift clock, and data inputs (pins 1 - 3, respectively), and must
reassemble the stored data from the serial output stream coming from pin 4. When the EEPROM is not
selected, its output is high impedance. R26 provides a positive level to CMOS buffer U5 in this case.
Input log amplifier of square-root electrometer.
The electrometer is a multi-stage circuit which produces an output voltage which is proportional to the
square-root of the input current. This is accomplished by three amplifier stages, AR1 (dual) and AR2,
having logarithmic and exponential responses. The nonlinear responses are generated by the fundamental
characteristic of bipolar transistors, which is represented in the following equations:
v =(nkT/q) log(I
be
where vbe = base-emitter voltage (volts)
n = emission coefficient (near 1.00)
k = Boltzmann's constant (1.38E-23 Joule/K)
T = Temperature (Kelvins)
q= electron charge (1.6E-19 coulomb)
l = collector current
c
I = saturation current
sat
e = base of natural logarithms
Input amplifier AR2 has an extremely high input impedance, with a bias current of only about
-15
40fA (40 x 10 A). All of the input current from J1 must therefore flow into the collector of Q1 (pin 8).
Negative feedback from the output of AR2 adjusts the base-emitter voltage of Q1 until precisely this current
flows into the collector. The output voltage from this stage, which is taken from the emitter of Q1 (pin 6), is
therefore v l = - (nkT/q) log(I
eb
The output voltage must be negative in order to forward-bias the base-emitter junction of Q1. However, the
negative power supply for AR2 is ground, so its output cannot go below ground. R4 and R5 provide about
700mV of negative offset, allowing the output of AR2 to remain positive, while Q1 is turned on. R5 also
stabilizes the loop gain at input currents near full scale (1µA), where the impedance looking into the emitter
of Q1 has dropped to 26k.
Since the non-inverting input of AR2 is grounded, the inverting input remains at ground also, keeping the
collector of Q1 at ground. This holds the collector-base voltage at zero, which is a necessary condition for
the equations above to apply. The input connection at J1 also remains near ground at low input currents,
SCION Instruments
/I + 1) or l = I (e(
c sat c sat
/I + 1).
in sat
436-GC/456-GC Service Manual Revision B February 2019
qv /nkT
be ) - 1),
610 Hardware description
Page: 81