Scion Instruments 436-GC Service Manual page 83

436-GC/456-GC
minimizing noise due to variations in input capacitance. R1 limits input current if an excessive voltage is
applied to the input, but it also allows the input voltage to rise slightly at the higher input currents.
R2, which isolates the amplifier input from the input cable capacitance for loop stability, has almost no DC
voltage drop across it, since only the bias current of AR2 flows through it. C3 also enhances loop stability,
and reduces high-frequency noise.
Because of the high impedance levels, this entire circuit must be shielded to work properly at all but the
highest input currents. It is also easily upset by test probes even when shields are in place. In any case,
the exact output voltage to be expected at a particular input current is unknown, since the saturation
current of the input log transistor is unknown. All that can be predicted is that the output voltage will
increase (in a negative direction) by about 26mV when the input current is doubled, or by 60mV when the
input current is raised by ten times, regardless of the specific current levels.
Reference current log amplifier.
The saturation currents of the individual transistors vary from one unit to the next, and also change rapidly
with temperature, doubling with each 10°C rise. In order to maintain stable and predictable calibration,
each transistor used in the anti-log stage must be balanced by a matching transistor in a log stage. The
anti-log stage uses two transistors, as will be described below, so a second log amplifier is needed for
compensation purposes. This stage consists of one section each of AR1 (pins 1-3) and Q2 (pins 6-8), and
is very similar to the input log amplifier.
The sum of the two emitter-base voltages of the log transistors is produced directly by connecting them in
series. The emitter of Q1 (pin 6) is connected to the base of the Q2 (pin 7), and the output Vsum is taken
from the emitter of Q2 (pin 6). The collector of Q2 (pin 6) is connected to the inverting input of AR1 (pin 2),
which is held at the same voltage as the noninverting input (pin 3). By connecting the base of Q2 (pin 7) to
the noninverting input, the collector-base voltage is forced to be zero. This causes the inverting input to
follow the output voltage of AR2 (pin 1). As this voltage varies by a few hundred millivolts over the full
range of the input current, the reference current (Tref) through R6 varies between 23 and 24 microamps.
The emitter-base voltage of Q2 is thus v
Q2 is:
AR1 is powered from the ±15V power supplies, which could cause avalanche breakdown of the emitter-
base junction of Q2, if the amplifier output ever approached the positive supply voltage. While this never
occurs in normal operation, even a momentary breakdown can cause a permanent increase in saturation
current. CR1 prevents the emitter voltage from rising to a destructive level during testing or other transient
fault conditions.
Anti-lot amplifier.
The logarithmically compressed voltage vsum is applied to an anti-log (or exponential) amplifier stage
which utilizes the other halves of matched dual transistors Q1 and Q2. Since the anti-log transistors are
connected in series, both collector currents are essentially equal. If we assume that all of the transistors
are at the same temperature T and have the same saturation current Ise, the base-emitter voltage of each
of the anti-log transistors will be half the value of vsum.
Their collector currents must then be I
the expression for v
SCION Instruments
eb
v - (nkT/q) log(I
sum
= - (nkT/q) log ((I
= I
c
above, we have
sum
L = I ( (1/2)log((lin/Isat + 1)(Iref/Isat + 1)) _ 1)
c sat e
= I (sqrt((lin/Isat + 1)(Iref/Isat + 1)) - 1)
sat
= sqrt (I + I )(I + I )) -I
in sat ref sat
= sqrt (( I + I )(I )) - I
in sat ref
436-GC/456-GC Service Manual Revision B February 2019
2 = - (nkT/q) log(I /I
ref sat
/I + 1) - (nkT/q) log(I
in sat
/I 1)(I / I 1)).
in sat ref sat
qv 2nkT
e-( sum/ ) - 1) from the equation in section 4. Substituting
sat
sat
(since I
sat
610 Hardware description
+ 1), and the net voltage at the emitter of
/I + 1)
ref sat
9
> 10 x I )
ref sat
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