Dma2D Reordering Features; Red And Blue Swap; Byte Swap; Table 5. Swap Operations - ST STM32L496 Series Application Note

New DMA2D features to support Intel 8080 displays
5.2

DMA2D reordering features

The DMA2D output FIFO bytes can be reordered to support the display frame buffer update
through a parallel interface (FSMC) directly from the DMA2D. The user can do combination
of reordering operations to get the right byte endianness aligned with the display color
coding.
5.2.1

Red and blue swap

The red and blue components can be swapped, this is done by setting the RBS bit in the
DMA2D_OPFCCR register.
This feature exists on the STM32L4 Series and STM32L4 Plus Series.
5.2.2

Byte swap

The MSB and the LSB bytes of a half-word are swapped in the output FIFO. This is done by
setting the SB bit in the DMA2D_OPFCCR register.
This feature is present only on the STM32L4 Plus Series.
Table 5 shows the swap operations required to match the LCD display color coding
depending on the display color depth and the bus interface width.
Color depth
8bpp (256 colors)
16bpp (64k colors)
18bpp (262k colors)
24bpp (16.7M colors)
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Table 5. Swap operations

Interface bus width
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
DocID029937 Rev 2
Required operation
Red blue swap
N
N
N
N
Y
Y
Y
Y
AN4943
Byte swap
N
Y
Y
N
N
Y
N
Y