Seco SM-C12 User Manual page 28

3.2.1.6 SPI interface signals
The signals related to SPI0 are as follows:
SPI0_CS0#: SPI primary Chip select, active low output signal. Electrical level +1.8V_S
SPI0_CS1#: SPI secondary Chip select, active low output signal. Electrical level +1.8V_S. This signal must be used only in case there are two SPI devices on the
carrier board, and the first chip select signal (SPI_CS0#) has already been used. It must not be used in case there is only one SPI device
SPI0_CK: SPI Clock Output to carrier board's SPI embedded devices. Electrical level +1.8V_S
SPI0_DIN: SPI0 Master Data Input, electrical level +1.8V_S. Input to i.MX 8M from SPI devices embedded on the Carrier Board
SPI0_DO: SPI0 Master Data Output, electrical level +1.8V_S. Output from i.MX 8M to SPI devices embedded on the Carrier Board
The signals related to QuadSPI are as follows:
ESPI_CK: QuadSPI Master Clock Output. Electrical level +1.8V_S. The reference timing signal for all the serial input and output operations
ESPI_CS0#: QuadSPI Master Chip Select Output. Electrical level +1.8V_S. Driven low by the processor to select the QuadSPI slave device on the carrier board. On
the same bus there is a second QuadSPI slave device (flash storage), mounted on the module, connected to a dedicated chip select signal
ESPI_IO_[0:3]: QuadSPI Master Data Bidirectional . Electrical level +1.8V_S. Data transfer between the master and slaves. In Single I/O mode, ESPI_IO_0 is the eSPI
master output/eSPI slave input (MOSI) whereas ESPI_IO_1 is the eSPI master input/eSPI slave output (MISO).
ESPI_RESET#: QuadSPI Reset. Output. Electrical level +1.8V_S. Reset the QuadSPI interface for both master and slaves.
ESPI_ALERT0#: Alert signal driven by the slave QuadSPI slave device. Input. Electrical level +1.8V_S
SPI interface can support speed up to 20MHz.
3.2.1.7 Audio interface signals
Here are following the signals related to I2S Audio interface:
AUDIO_MCK: Master clock output to Audio codec. Output from the module to the Carrier board, electrical level +1.8V_S
I2S0_LRCK: Left& Right audio synchronization clock. Bi-Directional between the module to the Carrier board, electrical level +1.8V_S
I2S0_SDOUT: Digital audio Output. Output from the module to the Carrier board, electrical level +1.8V_S
I2S0_SDIN: Digital audio Input. Input from the module to the Carrier board, electrical level +1.8V_S
I2S0_CK: Digital audio clock. Bi-Directional between the module to the Carrier board, electrical level +1.8V_S
All these signals have to be connected, on the Carrier Board, to an I2S Audio Codec. Please refer to the chosen Codec's Reference Design Guide for correct
implementation of audio section on the carrier board.
3.2.1.8 IC2 Interface
I2C_GP_CK: I2C General Purpose clock signal. Bi-Directional between the module to the Carrier board, electrical level +1.8V_S
SM-C12
SM-C12 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Authors: S.B. and L.G - Reviewed by N.P. - Copyright © 2019 SECO S.p.A.
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