Seco SM-C12 User Manual page 25

Smarc rel. 2.0 compliant module with nxp i.mx 8m applications processors
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3.2.1.1 LCD Display Support Signals
The panel control signals are:
LCD0_VDD_EN: Panel #0 VDD enable signal. Set high to enable. +1.8V_S electrical level Output.
LCD0_BKLT_EN: Panel #0 Backlight Enable signal. It can be used to turn On/Off the backlight's lamps of a connected LVDS display. +1.8V_S electrical level Output
LCD0_BKLT_PWM: This signal can be used to adjust the Panel #0 backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations. +1.8V_S
electrical level Output
LCD1_VDD_EN: Panel #1 VDD enable signal. Set high to enable. +1.8V_S electrical level Output
LCD1_BKLT_EN: Panel #1 Backlight Enable signal. It can be used to turn On/Off the backlight's lamps of a connected LVDS display. +1.8V_S electrical level Output.
LCD1_BKLT_PWM: This signal can be used to adjust the Panel #1 backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations. +1.8V_S
electrical level Output.
I2C_LCD_DAT: LCD I2C Data. This signal is used to read the LCD display EDID EEPROM. +1.8V_S electrical level Bidirectional
I2C_LCD_CLK: LCD I2C Clock: This signal is used to read the LCD display EDID EEPROM. +1.8V_S electrical level Output
3.2.1.2 Primary Display (LVDS Flat Panel) signals
ONLY ONE set of signals from the following two sets are present, dependent on the factory board configuration.
EITHER the signals for Channel #0 are LVDS:
LVDS0_0+ / LVDS0_0- : LVDS Channel #0 differential data pair #0
LVDS0_1+/ LVDS0_1-: LVDS Channel #0 differential data pair #1
LVDS0_2+/LVDS0_2-: LVDS Channel #0 differential data pair #2
LVDS0_3+/ LVDS0_3-: LVDS Channel #0 differential data pair #3
LVDS0_CK+/ LVDS0_CK-: LVDS Channel #0 differential Clock
OR the signals for Channel #0 are DSI:
DSI0_CLK+/DSI0_CLK-: DSI Channel #0 differential Clock.
DSI0_D1+/ DSI0_D1-: DSI Channel #0 differential data pair #1
DSI0_D2+/DSI0_D2-: DSI Channel #0 differential data pair #2
DSI0_D3+/DSI0_D3-: DSI Channel #0 differential data pair #3
The module has
LVDS1 interfaces of the edge connector. The MIPI-DSI 4 channels supporting one display. Supports resolution up to1920x1080p60, 1800x1200p60
Here follows the signals related to LVDS Channel #1 management:
SM-C12
SM-C12 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Authors: S.B. and L.G - Reviewed by N.P. - Copyright © 2019 SECO S.p.A.
one channel of the MIPI-DSI of the processor to the DSI0/LVDS0 and
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