Seco SBC-A62-J User Manual page 25

3.3.4 Optional Camera connector
Optional Camera connector - CN11
Pin Signal Pin
1 CSI_D1_DN
2 CSI_D1_DP
3 GND
4 GND
5 CSI_CLK0_DN
6 CSI_CLK0_DP
7 GND
8 CSI_D0_DN
CSI_CLK0 differential pair.
CSI0_MCLK: Master Clock, it is managed by i.MX6 pad P4. It is suggested, however, to use camera modules with onboard crystal / oscillator, and avoid using this
signal. Indeed, it could cause problems for EMI compliance requirements.
PWRON: external camera module Power enable signal. Managed by i.MX6 CSI0_DAT18 pin, it is a signal at electrical level 3P3V with a 4k7Ω pull-up resistor.
RESET: external camera module reset signal output. Managed by i.MX6 pad M6, it is a signal at electrical level 3P3V with a 4k7Ω pull-up resistor.
I2C3_SCL: general purpose I2C Bus clock line. Output signal, electrical level 3P3V with a 4k7Ω pull-up resistor. It is managed by i.MX6 processor's I2C3
controller. It is the same signal that is available also on Touch Connector J29.
I2C3_SDA: general purpose I2C Bus data line. Bidirectional signal, electrical level 3P3V with a 4k7Ω pull-up resistor. It is managed by i.MX6 processor's I2C3
controller. It is the same signal that is available also on Touch Connector J29.
SBC-A62-J
SBC-A62-J User Manual - Rev. First Edition: 1.0 - Last Edition: 2.3 - Author: S.B. - Reviewed by N.P. Copyright © 2016 SECO S.r.l.
Signal
9 CSI_D0_DP
10 GND
11 PWRON
12 CSI0_MCLK
13 I2C3_SCL
14 I2C3_SDA
15 RESET
16 3P3V
NXP i.MX6 Processor includes an Image Processing Subsystem, that can be used for video
applications, like video-preview, video recording and frame grabbing.
It is possible to access to the video input port through an FFC/FPC
connector, type HIROSE p/n FH12-16S-0.5SV(55) which is able to
accept 16 poles 0.5mm pitch FFC cables.
The pinout of this connector is shown in the table on the left.
Signals' description
CSI_D0_DN/CSI_D0_DP: CSI first input differential pair. It is managed by i.MX6 CSI_D0
differential pair.
CSI_D1_DN/CSI_D1_DP: CSI second input differential pair. It is managed by i.MX6 CSI_D1
differential pair.
CSI_CLK0_DN/CSI_CLK0_DP: CSI Clock input differential pair. It is managed by i.MX6
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