LG CED-8042B Manual page 73

2. Signal Flow Diagram
P/U UNIT
5
R-C
PUVC HAVCADJ
(DAC)
A ~ H
I/V AMP
+3V
FVREF
FPDOUT
FPDIN
W/XR,ODON (WR)
LDON(CPU)
VRDC
VC2V
VREF
VWDC2(DAC)
VWDC
4
VWDCN
VRDC
RREF
VWDC
Control
VRDCN
VRDC
WLDON
WREN
(WR)
WR/RE
(CPU) WRHLD
XMRST
(CPU)
RFGUP
(WR)
RPOWER WPOWER
(DAC) (DAC)
3
SPINDLE DRIVE
HU+, HU-
HV+, HV-
HW+, HW-
U, V, W
LB11995H
COMPENSATOR
VCC2,3 : 12V
VCREF : 2.5V
2
ACTUATOR, SLED, & TRAY DRIVE
VREFOUT : 2V
VREFIN : VC2V
FCS+, FCS-,
LA6543M
TRK+, TRK-
TRYLD+, TRYLD-
SD+, SD-
1 H1+, H1-, H2+, H2-
SLED FG
SPEED GEN.
AMP
HALL BIAS ( DAC )
A B
OPC
ROPC
RESAMP
ROPC2 (RICOH)
AUX1,2,3 GUP1 RFGUP (WR)
GUP2,3* ATIPGUP*, AGCON
AGCON
RECD1, RECD2
/AKCS, SCLK, SDATAO
LPF
TEIN
AK8563
TE
LPF TE
(RF)
FE LPF
FE
CDR/RW (LAT)
WRHLD
A,B,C,D
E,F,G,H
XTOR (P/U) DRC
RRF
AMP
LPF LPF
RFDC(DSP)
RFOSADJ(DAC)
WREN(WR)
CE_OFFSET (DAC )
DFCT2 RFAC CE
(DSP) (DSP)
PWRCTL1
12V, 5V(A),
4V, 2.5V, VC2V
SPNON
SPNFG
SPN8/12CM, SPN_PHASE, SPN_BOOST
MDP(DSP)
SW
&
OP-AMP
MPW(RICOH)
DMCON (RICOH)
XTSL (LAT)
SPNREV, SPNFG
SBRK (RICOH) RFDC(RF)
RFAC(RF)
12V, 8V,
5V(D), VC2V
ACT_MUTE(CPU)
TRAY_MUTE(LAT)
TRAY_CTL(DAC)
FAO, TAO, SAO
SAO
SUMMING
SLDOFFSET ( DAC )
AMP
SLD_MOVE( CPU )
SLD_OUT
SW
HALL1
SLDFG(CPU)
SLDSEL (LAT)
C
WFPDSH, RFPDSH, MPDSH, SPDSH,WBLSH ,WLDON,W/XR,ODON
ASYM1, ASYM2
BLEVEL0,2
CDR/RW
ASYMCLR
(LAT)
ADC BLOCK
VC2V
MPXO
SLDADJ
VC2V
MIRR
MPXO
SLDADJ
H8/3062
(CPU)
FWE_ON
MIRR_RRW
DACS
SCLK
SDATAO
SA6, SA7
SD[7:0}
/SWEB
/CSMOD
74HC374 /EPCS
&
SCLK
DECODER
SDATAO
(LAT)
RRWMODE
(LAT)
VC2V
CXD3011R-1
(DSP)
DFCT
SLDADJ
(CPU ADC)
PEAK
VCO FILTER
DETECT
XX
WRHLD(RF)
D E
79 80
SW
5V(H),3.3V
RFCK(DSP)
WR/RE (LAT)
SD[7:0], SA[7:0](DATA LINE & ADDRESS)
/CS0RL, /CS1RL, /SREB ,/SWEB
SRDY, SINT0, SINT1
MONIT
/EJECT_KEY, /PLAY_KEY
RL5E808
/LOAD_SW, /OPEN_SW
(RICOH)
MA/SL
MD2
FLASH
FWE
WRITE
SPINDLE DRIVER SPREV (REVDET) SPFG(FGIN)
MPWM, SPBRK(SBRK) DMCON
12Ch-DAC
BUFFER
DAMON WPOWER
VWDC2 HBIAS
(2M)
SLDOFFSET CE_OFFSET
DAC
RFOSADJ VC_REF
HAVCADJ RPOWER
TRAY_CTL
(A, D, L, H, AD) 5V
EEPROM SDATAI (CPU)
MIRR_RRW VC2V
WFCK, LRCK, BCLK, MDATA
*
SW SW
C2PO, SCOR
SBSO
VC_CE_OFFSET
( CPU ADC )
EXCK
AUDIO CONTROL
AUD_MUTE(CPU)
AO1F, AO1R, AO2F, AO2R, AUGND
SERVO ERROR INPUT
LPF
SE
TE
FE,TE,CE LPF
INV
DFCT2
DEFECT DETECTION
F
RFGUP
(RF)
WRITE
CDR/RW
H/W ODOFF
EFM1
WR/RE
EFM2
(LAT)
ENCEFM
WGATE
ROPC1
RESAMP
ATAPI
HOST I/F
POWER SOURCE
PWRCTL1
12V
( ACT DRV ) 8V
POWER
(DSP) 4V
SOURCE
(RICOH) 3.3 V
2V, 2.5V
2V
AMP
SAO
VC_REF(DAC)
SW CE
SLDSEL (LAT)
LOUT
AUGND
ROUT
AUDIO
CONTROL
DOUT
FE, TE, CE (RF)
G H