LG CED-8042B Manual page 22

Buffer Memory Interface
Pin No. Pin Name
92, 93, 94,
95, 97, 98,
RA [11 : 0]
99, 100, 102,
103, 104, 105
107 ROEB
108 RRAS0B
109 RCAS1B/
RWE1B
110 RWE0B
111 RCAS0B
113, 114, 115,
116, 118, 119,
120, 121, 123, RD [15 : 0]
124, 125, 126,
128, 129, 130,
131
Monitor
Pin No. Pin Name
9 MONIT0
IN Input Pin
OUT Output Pin
I/O Input/Output Pin
IN (PU) Input Pin with Internal Pullup Resister
IN (PD) Input Pin with Internal Pulldown Resister
I/O (PU) : Input/Output Pin with Internal Pullup Resister
I/O (PD) : Input/Output Pin with Internal Pulldown Resister
OUT (TS) : Three State Output Pin
OUT (OD) : Open Drain Output Pin
OUT (PU, TS) : Three State Output Pin with Internal Pullup Resister
Type
OUT (TS) RAM ADDRESS : Address for DRAM
These pins are multiplexed address output.
OUT (TS) OUTPUT ENABLE : OE for DRAM
OUT (TS) ROW ADDRESS STROBE 0 : RAS for DRAM
OUT (TS) COLUMN ADDRESS STROBE 1/WRITE ENABLE 1 : CAS1/WE1 for DRAM
In case of 16 bit data bus is selected, set CAS decode or WE decode by setting
internal registers.
WRITE ENABLE 0 : WE 0 for DRAM
OUT (TS)
Write strobe in case of 16 bit data bus is selected.
OUT (TS) COLUMN ADDRESS STROBE 0 : CAS0 for DRAM
In case of 16 bit bus size is selected, this pin is used by a strobe.
I/O (PU) RAM DATA : Data for DRAM
Possible to set bus size (16 bit/8bit) by setting internal registers.
Type
Monitor 0 : Monitor pin
OUT
This pin is as follows by setting register 0X3E.
Description
Description
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