Operation Principle And Function Circuit; Fig. 3-5. Block Diagram - L-Card L-502-P-G-D-I User Manual

31

3.4. Operation principle and function circuit

CONV_IN, START_IN
CONV_OUT, START_OUT
DI_SYN1, DI_SYN2
X1...X16, Y1...Y16, GND32
Flash
Flash-
Memory
памяти
Node
2 МБ
Джампер
Backup data
резервной jumper
загрузки
FPGA is the basic logical element in the L-502, in which all the interface functions, the
hardware logic of ADC calibration, and the logic of the secondary synchronization are concentrated
3.3.5
( )
Flash-memory with a capacity of 2 MB is designed to store the main and backup firmware
FPGA, calibration factors, serial number. Half the amount of Flash memory is provided for user
tasks.
The L-502 I/O subsystem includes nodes for the channel switch, ADC, DAC (L-502-░-░-D),
digital I/O, and primary synchronization circuit (
The galvanic isolation unit (L-502-░-G-░) isolates all circuits of the I/O subsystem from
circuits connected electrically to any circuits of the computer.
The ADSP-BF523 signal processor (L-502-P-░-░) is designed for additional data processing
and control. If the processor is enabled, the entire data stream and the I/O subsystem are transferred
through the processor's I/O ports. For example, it is possible to create a control loop through a
Подсистема
I/O
ввода-вывода
sub-system
Комму-
Switch
татор
Узел
2MB

Fig. 3-5. Block diagram

3.4: Operation principle and function circuit
Схема
L-502 primary
первичной
synchronization
синхронизации
scheme
L-502
АЦП
ADC
Узел гальвано-
Galvanic isolation
развязки
node
Схема
ADC secondary
вторичной
synchronization
синхронизации
data scheme
данных АЦП
FPGA
Cyclone IV
PCIe
3.3.5
).
Только для L-502- - -D
Only for
ЦАП DAC1, DAC2
DAC
DO1...DO16
Цифровой
Digital
в/в
O/I
DI1...DI16
Только для L-502- -G-
Only for
Только для L-502-P- -
Only for
Порты
O/I ports
в/в
HOST
DMA
JTAG
ADSP-
BF523
SDRAM
32 МБ
32 MB