E20-10 Operating Principle - L-Card E20-10 User Manual

Digital output register DO1...DO16 sets exactly parallel 16 -bit data on TTL-outputs for
programmable controllability of the third outputs state as well as for controllability of the third state
on signal EN_OE (table
START acquisition start synchronization input-output. If digital line DI16 for input
asynchronous function is not active, then this digital line may be set in software to functions
"master" (output) or "slave" (input) of START signal. These features can be used, for example, for
multi-module synchronization of data acquisition start for several E20-10 according to diagram
"one master – some slaves" (p. 5.2.2).
Digital input-output of ADC synchronization frequency SYNC can be used fro multi-module
synchronization of ADC conversion frequency synchronization of several E20-10 according to
diagram "one master – some slaves" (p. 5.2.2).
Voltage converter converts unstable input voltage of +9V...+27V into stable power supply
voltages for internal nodes of E20-10. Auxiliary voltage of ±12V is output from transmitter output
to analog outputs connector of module E20-10 for external device power supply.
LED indicator (not shown on diagram, output to front panel of module) is controlled
directly from AVR. Connection conditions on USB and other events are signalized by mode and
color of emission, details see in Programmer's manual [1].

5.2. E20-10 operating principle.

USB-module E20-10 does not use power supply circuit of USB 2.0 interface. To switch on
module it is required to apply power voltage of +9.0V...+27V to it
6.3.1) from network card including in delivery package (p. 3.3.1) or from external constant-voltage
source. Power supply circuit parameters for E20-10 see in p. 7.4.
Upon switching on the program of USB-device upgraded in AVR completes procedure on
connecting on USB as soon as computer connection will be detected.
Upon successful detecting of E20-10 by your computer operating system the
ready to operate on level of software applications using delivered by L-Card library functions, in
particular, one of these functions is FPGA E20-10 downloading – this download is required to be
performed once upon as E20-10 switching on (see Programmer's manual [1]).
At the close of FPGA download from software level all information about this module E20-
10, in particular, serial number, module revision, AVR firmware version, FPGA firmware version
will be available.
Prior to start data acquisition it is required to configurate it in software, because you may not
change configuration settings during data acquisition. Main configuration parameters are:
• ADC conversion frequency (within the range of from 1.0 to 10 MHz).
• Data acquisition frame size: frame size, interframe delay duration Number of sampled
input channels can be flexible configurated from 1 to 4. ADC conversion frequency is
divided among sampled channels in accordance with their quantity and sampling order
(frequency). The required sampling order of channels forming the frame is previously
recorded in control list with size of from 1 to 256 ADC paths, m. When data acquisition
the numbers of channels are repeatedly read with given ADC conversion frequency
(1...10MHz) and are sent to dynamic commutator as control signal. To achieve data
acquisition lower frequencies the interframe delay is programmed which allows to achieve
lower data acquisition frequencies. Under given nonzero interframe delay upon
completion of control list access cycle (in frame completion) the relevant number of
12
On trigging E20-10 power supply voltage should be min. +9.5 V.
13
device driver installation is performed under first-time connecting (p.
E20-10
6-2).
12
through power connector (p.
4.2
)
13
module is
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