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(1)
(7)
BLOCK4
FPGA+RTC+ESVM
@bloc
(8)
(17)
(18)
(22)
(23)
(27)
(28)
(32)
(33)
(41)
(42)
(43)
BLOCK7
(48)
(49)
RS232_nDCD2
CLK_SD_33.33MHz
RS232_nDSR2
SD0_nRESET_SOFT
RS232_nDTR2
RS232_DCD2_CON
RS232_RXD2
RS232_DSR2_CON
RS232_TXD2
RS232_DTR2_CON
RS232_nCTS2
RS232_RXD2_CON
(55)
RS232_nRTS2
RS232_TXD2_CON
RS232_CTS2_CON
(56)
SD0_CD
RS232_RTS2_CON
SD0_WP
SD0_nDRQ
(59)
SD0_DACK
SD&RS232
(60)
MCCLK
(61)
MCDAT
@bloc
(62)
MCCMD
(63)
(64)
(65)
CLK_32.768kHz
(66)
CLKIO_66.66MHZ
(67)
nLOS_FPGA
nHALT_FPGA
RINGER_SYNC_FPGA
nBATT_FPGA
DC_ALM_FPGA
AC_ALM_FPGA
nFAN_ALM_FPGA
SHELF_nFAN_ALM_FPGA
LED_RUN_FPGA_DRIVE
LED_ALM_FPGA_DRIVE
CT_D[0]
CT_C8
CT_FRAME
SVM_DSP_OUT[1]
SVM_DSP_OUT[0]
LUHW_VOX_CODEC
HWFH_NEXUS
LUHW0_NEXUS
LDHW0_NEXUS
HW_CLK0_NEXUS
CH_SEL[5]
CH_SEL[6]
CH_SEL[7]
RMT_nRESET_SOFT
NEXUS_nRESET_SOFT
CL3146
nBUSY
CL3207
RTC_nINT
BANK[0-2]
UCFG[0-3]
+3.3VD
+3.3VD
+3.3VD
DG
DG
DG
ESVM_VOX
CL3203
CL3204
CL3156
CL3157
CL3158
CL3159
CL3160
CL3161
VOX[0-3]
MELODYSEL
MOHSEL
SRAM_nWR
Mu/nA
SRAM_nBC1
SRAM_nBC0
EC_AD[0-15]
EC_AD[0-15]
SRAM_nCS
EC_PAR
MEMORY_CARD_PRESNT
EC_nCBE1
RMT_nRESET_SOFT
EC_nCBE0
nRESET_SOFT
EC_nFRAME
@bloc
CLK_NEXUS_66MHz
EC_nPERR
EX2_A[0-21]
EX2_D[0-15]
EC_nSTOP
EX2_nDR
EC_nTRDY
nWE1
EC_CLK
nWE0
EC_nCDET
nBS
EC_nINT
nBUSY
CT_D[0-7]
CT_NETAEF
nCS_NEXUS
CT_C8
nCS_SRAM
BLOCK8
CT_FRAME
EXT_nINT0
RINGER
NEXUS(+SRAM)
BANK[0-2]
UCFG[0-3]
MASTER/nS
nBACK
M/nS
nBREQ
POWER_TYPE1
NEXUS_nINT
POWER_TYPE0
nRESET_POWER
+3.3VD_B
DG
+3.3VD_B
+3.3VD
+3.3VD
nBAT_ALM
TP_DRAM_VREF
KX-NCP500GR IPCMPR CARD DETAILED BLOCK DIAGRAM (2/2)
11
BLOCK10
CL3190
nLOS_FPGA
nLOS_FPGA
CL3191
nHALT_FPGA
nHALT_FPGA
CL3192
RINGER_SYNC_FPGA
RINGER_SYNC_FPGA
CL3193
nBATT_FPGA
nBATT_FPGA
CL3194
DC_ALM_FPGA
DC_ALM_FPGA
AC_ALM_FPGA
CL3195
AC_ALM_FPGA
nFAN_ALM_FPGA
CL3196
nFAN_ALM_FPGA
CL3197
SHELF_FAN_ALM_FPGA
SHELF_nFAN_ALM_FPGA
LED_RUN_FPGA_DRIVE
CL3198
LED_RUN_FPGA
LED_ALM_FPGA_DRIVE
CL3199
LED_ALM_FPGA
EC_nRST
LDHW[1]
LUHW[1]
SHW_CLK
SHW_FH
BLOCK15
+15V
SVM_DSP_OUT[1]
SVM_DSP_OUT[1]
SVM_DSP_OUT[0]
+15V
SVM_DSP_OUT[0]
LUHW_VOX_CODEC
+15V
LUHW_VOX_CODEC
+3.3VD
HWCLK[0]
LDHW[0]
+3.3VD
+3.3VD
CH_SEL[6]
DG
CH_SEL[7]
VOX[0-3]
DG
VOX[0-3]
@bloc
Mu/nA
VREF_7.5V
VREF_7.5V
DG
CODEC
BLOCK9
+15V
HW_CLK[0]
VREF_7.5V
HWCLK[0]
LDHW[0]
+15V
LDHW[0]
LUHW[0]
+15V
LUHW[0]
CH_SEL[1]
+3.3VD
CH_SEL[1]
CH_SEL[0]
CH_SEL[0]
+3.3VD
+3.3VD
@bloc
DG
DG
CL3162
MELODYSEL
MELODYSEL
CL3163
MOHSEL
DG
MOHSEL
CL3164
Mu/nA
Mu/nA
EC_AD[0-15]
CL3165
EC_PAR
EC_PAR
CL3166
EC_nCBE1
EC_nCBE1
EC_nCBE0
CL3167
EC_nCBE0
CL3168
EC_nFRAME
EC_nFRAME
CL3169
EC_nPERR
EC_nPERR
EC_nSTOP
CL3170
EC_nSTOP
CL3171
EC_nTRDY
EC_nTRDY
EC_CLK
CL3172
EC_CLK
CL3173
EC_nCDET
EC_nCDET
CL3174
EC_nINT
EC_nINT
CT_D[0-7]
CT_D[0-7]
CL3175
CT_NETAEF
CT_NETAEF
CL3176
CT_C8
CT_C8
CL3177
CT_FRAME
CT_FRAME
CL3178
RINGER
RINGER
CL3179
MASTER/nS
MASTER/nS_FPGA
CL3180
M/nS
M/nS_FPGA
CL3181
POWER_TYPE1
POWER_TYPE1_FPGA
CL3182
POWER_TYPE0
POWER_TYPE0_FPGA
RS232_DCD2_CON
CL3183
RS232_DCD2_CON
CL3184
RS232_DSR2_CON
RS232_DSR2_CON
CL3185
RS232_DTR2_CON
RS232_DTR2_CON
CL3186
RS232_RXD2_CON
RS232_RXD2_CON
RS232_TXD2_CON
CL3187
RS232_TXD2_CON
CL3188
RS232_CTS2_CON
RS232_CTS2_CON
CL3189
RS232_RTS2_CON
RS232_RTS2_CON
+15V_CON
TP_+15V_CON
+15V_CON
+3.3VD_BB
TP_+3.3VD_BB
+3.3VD_BB
+3.3VD
+3.3VD
+3.3VD
DG
DG
+15V
DG
+2.5VD
TP_+15V
+3.3VD_B
TP_+3.3VD_B
+3.3VD
POWER
+15V
TP_+3.3VD
+15V_CON
+15V
+3.3VD_B
+3.3VD_BB
+3.3VD_B
+3.3VD
+3.3VD
+2.5VD
nBAT_ALM
+2.5VD
+1.8VD
+1.8VD
nRESET_POWER
HARD_nRESET_SW+1.25VD
+1.2VD
DRAM_VREF
DG
@bloc
BLOCK13
DG
KX-NCP500GR
@bloc
TP_+2.5VD
+1.8VD
TP_+1.8VD
+1.25VD
TP_+1.25VD
+1.2VD
+1.25VD
TP_+1.2VD
+1.2VD
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