Siemens SITOP Series Function Manual page 21

Note
All the addresses in decimal values should be converted into hexa decimal format when
they are assigned to FB.
Note
Requirements for reading cyclic data
If the addresses of the configured modules are outside the process image address range,
then the function block cyclic data parameters will be assigned to "zero" values.
In order to avoid this problem, you can:
1. Increase the process image input size or change the addresses of the modules to
2. Use peripheral addressing. For this you need to add ":P" in the function blocks where
Preferably, it is recommended to use first solution, because process image has following
advantages:
• This is part of CPU system memory and updated periodically by CPU.
• Advantages of the process image access compared to direct access to the
• Process image comparatively takes less time to access. For example, CPU 317-2 DP
• Bit addressing is possible.
For more details, please refer to the links below:
• https://support.industry.siemens.com/cs/document/18325417/where-and-when-do-
• https://support.industry.siemens.com/tf/WW/en/posts/increasing-pip-piq-vs-peripheral-
4. Function blocks and input parameters are slightly different for 1200/1500 and 300/400
PLCs. Cyclic Input and output addresses are represented by single hardware identifier in
1200/1500 PLCs, whereas cyclic input and output addresses are different for 300/400
PLCs. For any input parameter with
(
For any output parameter with
(
SITOP PSU8600 Firmware V1.4: Faceplates and Communication Blocks V2.4 for SIMATIC STEP 7 V14 SP1, V15 and V15.1 (TIA)
Function Manual, 11.2018, A5E37763954-09-76
keep the address in process image range.
"%IW" instructions are there.
input/output modules, offers the advantage that a consistent image of process signals
is made available to the CPU during cyclic program processing. If the signal state at
an input module changes during program execution, the signal status in the process
image is maintained until the process image is updated in the next cycle. Moreover,
since the process image is stored in the CPU's system memory, access to the process
image is significantly faster than direct access to the signal modules.
takes 0.05 μs with process image and 15.01 μs with peripheral addressing.
you-need-peripheral-addressing-?dti=0&lc=en-WW
addressing/62626?page=0&pageSize=10
Cyclic_IO_IN_HeadModule_address
Cyclic_IO_OUT_Output1_address
5.2 FB SITOP_PSU8600/SITOP_PSU8600_1
Cyclic_IO_IN_<submodule>_address
), cyclic input address needs to be given as the input.
Cyclic_IO_OUT_<submodule>_address
), cyclic output address needs to be given as the ssinput.
SIMATIC STEP 7 function blocks
21