Main Operating Voltages; Power-On/Power-Down Reset (Por/Pdr); Table 1. General Operating Conditions; Figure 2. External Capacitor - ST STM8S Application Note

Power supply
2.2

Main operating voltages

STM8S devices are processed in 0.13 µm technology. The STM8S core and I/O peripherals
need different power supplies. In fact, STM8S devices have an internal regulator with a
nominal target output of 1.8 V.
Stabilization for the main regulator is achieved connecting an external capacitor C
V pin. C
CAP
less than 15 nH.
Table 1.
Symbol
C
EXT
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
temperature, DC bias and frequency in addition to other factors.
Figure 2.
Where:
ESR is the equivalent series resistance
ESL is the equivalent inductance
2.3

Power-on/power-down reset (POR/PDR)

The input supply to the main and low power regulators is monitored by a power-on/power-
down reset circuit. The monitoring voltage range is 0.7 V to 2.7 V.
During power-on, the POR/PDR keeps the device under reset until the supply voltages (V
and V
DDIO
At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a
reset release is defined in the electrical characteristics section of the product datasheet.
A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall.
The POR/PDR also generates a reset when the supply voltage drops below the V
threshold (isolated and repetitive events).
Recommendations
All pins need to be properly connected to the power supplies. These connections, including
pads, tracks and vias should have the lowest possible impedance. This is typically achieved
with thick track widths and preferably dedicated power supply planes in multi-layer printed
circuit boards (PCBs).
In addition, each power supply pair should be decoupled with filtering ceramic capacitors (C)
at 100 nF with one chemical C (1..2 µF) in parallel on the STM8S device. The ceramic
capacitors should be placed as close as possible to the appropriate pins, or below the
appropriate pins, on the opposite side of the PCB. Typical values are 10 nF to 100 nF, but
8/42
is specified in Table
EXT
General operating conditions
Parameter
V external capacitor
CAP
External capacitor
ESR
) reach their specified working area.
Doc ID 14651 Rev 3
1. Care should be taken to limit the series inductance to
Conditions
0.05 ≤ ESR ≤ 0.2 Ω at 1 MHz
(1)
C
Rleak
AN2752
to the
EXT
Min Max Unit
470 1000 nF
ESL
DD
POR/PDR