NXP Semiconductors S32R27 Hardware Design Manual
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NXP Semiconductors S32R27 Hardware Design Manual

NXP Semiconductors S32R27 Hardware Design Manual

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NXP Semiconductors
Application Note
S32R27/37 Hardware Design Guide
by: NXP Semiconductors

1 Introduction

The S32R is a 32-bit heterogeneous multi-core microcontroller
family primarily intended for use in computationally intensive
automotive RADAR applications. The device family
incorporates Power Architecture
independent e200z7260 for general computation and the
S32R274 device also features an e200z420 core with an
e200z419 checker core running in delayed lockstep
configuration for safety-critical and housekeeping tasks. The
family integrates high-performance signal processing features
designed to support sophisticated automotive RADAR
applications, and the S32R274 also integrates high accuracy
analog features to further enhance it's ability to interface with
a wide range of RADAR RF devices.
This application note illustrates the S32R family power supply
options and details the external circuitry required for power
supplies, oscillator connections, and supply decoupling pins. It
also discusses configuration options for clock, reset, ADC
modules and the RADAR analog front-end, as well as
recommended debug and peripheral communication
connections (including MIPI-CSI2) and other major external
hardware required for the device.
The S32R family requires multiple external power supplies to
operate. The main cores internal logic requires a 1.25 V power
supply. This can be supplied from an external source or on
some devices this can alternatively be provided by an internal
DC-DC regulator that requires a dedicated supply. 3.3 V is
®
cores arranged as two
Document Number: AN5251
Contents
1
Introduction.............................. .............................. 1
2
overview.................................................................. 2
3
Power supply...........................................................3
4
Clock configuration...................... .........................15
5
Device reset configuration............... .....................17
6
connector pin-out definitions.................... ............ 18
7
ADC overview........................... ........................... 22
8
RADAR analog front end................. .................... 23
9
connections.......................................... ................. 29
10
High speed layout considerations..........................48
A
Revision History........................ ........................... 49
Rev. 1, 04/2018

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  • Page 1: Table Of Contents

    NXP Semiconductors Document Number: AN5251 Application Note Rev. 1, 04/2018 S32R27/37 Hardware Design Guide by: NXP Semiconductors Contents 1 Introduction Introduction............1 S32R family package options The S32R is a 32-bit heterogeneous multi-core microcontroller overview..............2 family primarily intended for use in computationally intensive automotive RADAR applications.

  • Page 2: S32R Family Package Options Overview

    Wave Generator Module None None (WGM) LINFlexD Yes, 1 module Yes, 1 module None FlexPWM 1 module, 12 channels 1 module, 12 channels 1 module, 11 channels Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 3: Power Supply

    Aurora I/O, and MIPI-CSI2. Detailed information on the power management configurations can be found in the Power management controller section. 1. Not available on the S32R372 141BGA Package. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 4 0.1 μF x 16, 4.7 μF x 4, 10 μF x 2 (40 μF total) VDD_HV_IOx 3.3 V 2 x 0.1 μF for each VDD_HV_IO supply Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 5 5. VDD_LV_DPHY 6. VDD_LV_CORE 7. VDD_LV_AURORA 8. VDD_HV_PMU 9. VDD_HV_FLA 10. VDD_LV_LFASTPLL 11. VDD_LV_IO 12. VDD_HV_PWM 13. VDD_HV_IO 2. Not present on S32R372 141MAPBGA Package 3. Not present on S32R372 141MAPBGA Package S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 6 4. This interface is not present on the S32R372 device, but the supply name remains the same for the 257MAPBGA package to avoid confusion, and is not present on the 141MAPBGA package. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 7 100 Kilo Ohm resistor can be connected between VDD_HV_REG3V8 and the PMOS gate. 5. Not supported on S32R372 141MAPBGA package. 6. VREG_SEL pad is internally bonded to GND on S32R372 141MAPBGA package. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 8 This can assist in cases where the power supply reaches the minimum LVD threshold but then drops below the threshold again when loaded, before reaching a stable regulation point. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 9 Component Label Recommended Value SI3443, 2SQ2315 2.2 μH 3A <100 mΩ series resistance (E.g. Bourns SRU8043-2R2Y) SS8P3L 8A Schottcky diode 24 kΩ 10 μF ceramic Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 10 VREG_SWP net until it reaches the PMOS switch. Nets on other PCB layer should avoid running parallel to this net. The figure below is a circuit schematic showing an example SMPS circuit derived from the above guidelines. For best performance, use the component values recommended in Table S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 11 • VDD_LV POR function (can be enabled by software) • VDD_LV LVD/HVD circuits (can be enabled by software) 8. Not required on S32R372 141MAPBGA package as VREG_SEL is internally bonded to GND S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 12 It is rather a guarantee that the device will recover if this level is crossed. 9. Not required on S32R372 141MAPBGA package as these signals are internally bonded. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 13 • VDD_HV_FLA • VDD_HV_ADC 10. As mentioned previously, the internal POR management is disabled by default when external regulation mode is selected. They cannot be disabled when operating in internal VREG mode. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 14 3.5.3 Brown-out management During brown-out, the device re-enters the POWER-UP phase as soon as the threshold of either POR VDD 1.2 V or APOR is crossed. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 15: Clock Configuration

    PLLs. In order to minimize any potential noise, it is recommended that the additional capacitors recommended in Table 5 are fitted to the VDD_LV_PLL0 supply. 11. Divided by 2 (160 MHz), and 4 (80 MHz) if used for system and peripheral clocks S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 16 Care should be taken during PCB design to avoid vias, and ensure that all differential pairs are trace and impedance matched, and also follow differential pair best practices as detailed later in the document. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 17: Device Reset Configuration

    Both of these pins operate on the 3.3 V power domain. 12. Note that VREG_POR_B remains active in internal regulation mode. As such, if it is pulled low it will cause a power-on reset in the device. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 18: Recommended Debug Connectors And Connector Pin-Out Definitions

    GND/VSS EVTO0 JCOMP 1. If LBIST is enabled, an external pull resistor between 1 Kilo and 100 Kilo Ohm must be connected between TCK and either VDD/VSS to avoid LBIST failures S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 19 "even" side of the connector be mounted closer to the edge of the printed circuit board to facilitate a direct connection to the tool. Figure 12 is courtesy of Samtec U.S.A. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 20 TCK/TCKC/DRCLK TMS/TMSC/TxDataP TX1+ TDI/TxDataN TX1- TDO/RxDataP JCOMP/RxDataN TX2+ EVTI1 TX2- EVTI0 EVTO0 TX3+ VREG_POR_B TX3- RESET_B (TX4+) CLK+ (TX4-) CLK- (TX5+) EVTO1/RDY (TX5-) 1. Reserved for TXn signals, not currently used. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 21 A pullup resistor prevents debug mode from being forced after reset if debug mode is enabled (JCOMP = high). It also prevents breakpoints from being forced if debug mode is enabled. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 22: Adc Overview

    There is an analog bypass bit "APC" in the Multiplexed Signal Configuration Register (MCSR) registers of the System Integration Unit (SIUL2) for the pins to disable the digital circuitry from the analog pins. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 23: Radar Analog Front End

    • Sigma-delta PLL (SDPLL) producing 320 MHz/160 MHz/80 MHz clocks for AFE components • Low phase noise, low (1-2ps) jitter 40 MHz oscillator (XOSC) S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 24 SDPLL Output 320 MHz, 160 MHz, Output 80 MHz clocks Pair Modulator Output Filtered Output Decimation 14 bits x4 Filters Conversion Filter Enables Complete x4 Figure 14. AFE Wrapper block diagram S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 25 Bypass capacitor rampDAC 2.5 V VREG 1.0 μF & 0.1 μF grounded to VSS_HV_REGDAC 8.2 Sigma-Delta ADC The four time-continuous SD ADCs receive input as a differential pair. Each instance has two dedicated input pins. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 26 The DAC is used to produce analog ramp signals for generation of RADAR waveforms. Table 18. DAC signal description Name Pin (257MBGA) Direction Function DAC_AN DAC negative output (current) Connected to external 300 Ohm resistor Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 27 Instructions on how to connect an external source to drive the XOSC clock can be found in Connecting external clock sources. Table 19. XOSC external connections Name Pin (257MBGA) Pin (141BGA) Direction Function XOSC_EXTAL EXTAL analog input signal XOSC_XTAL XTAL analog output signal S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 28 Differential clock supplied from external differential source - or + VDD_LV_SDPLL 0.1 & 1 μF Capacitor to Ground VSS_LV_SDPLL Tied to Ground VDD_LV_SDCLK 0.1 & 1 μF Capacitor to Ground VSS_LV_SDCLK Tied to Ground Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 29: Example Communication Peripheral Connections

    HOST-T2 SCI_RXDA2 RIN2 ROUT2 SCI_TXDA2 HOST-R2 DOUT2 DIN2 SCI_TXDA HOST-R1 DOUT1 DIN1 SCI_RXDA HOST-T1 RIN1 ROUT1 0.1uF 0.47uF DB9F 0.47uF 0.1uF 3.3V or 5V Figure 17. Typical SCI to RS232 circuit S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 30 Only a single wire is required for communication and is commonly included in the vehicle wiring harness. Figure 18 shows a typical interface implemented using the NXP MC33661 LIN transceiver. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 31 VSUP Input Power Supply Protected battery This is the power voltage supply for the device and is typically connected to a nominal 12 V Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 32 4-pin vertical connector with pegs for target system, tin contacts, with latch 39-29-9042 4-pin right-angle connector with flange for target system, gold contacts, latch 39-29-5043 Mating connector with latch for cable assemblies 39-01-2040 Socket terminal for mating cable assembly 39-00-0077 S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 33 4700 pF 33pF 33pF 47nF TJA1080ATS/1 INH1 47pF INH2 51μH MCU FR_x_TX MCU FR_x_TXEN MCU_GPIO TXEN MCU FR_x_RX ERRN WAKE MCU GPIO +3.3V RXEN TRXD0 STBN TRXD1 Figure 19. Typical FlexRay circuit S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 34 (low to MCU GPIO enter Low-power mode). Internal pulldown. TRXD1 Input/Output Data bus line 1 Tie low Data bus signal 1 for an inner star connection Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 35 The DB9 connector allows for 2 channels on a single connector. The dual channels allows for a redundant wiring for increased reliability. The dual channel capability is built into the FlexRay standard. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 36 A male type connector is used on the evaluation board and a female type cable connects with this. The metal shell of the connector should be connected through a ferrite bead to GND. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 37 However, the value of this resistor may limit the maximum speed of the CAN module if not sized properly for the speed. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 38 60 Ω MCU_CAN_TXD CANL CANL MCU_CAN_RXD MCU_3.3V 4700 pF 4700 pF 4700 pF TJA1057GT(K)/3 10 μF Figure 22. Typical CAN FD circuit using TJA1057 NOTE • Decoupling shown as an example only. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 39 A socket is used on the evaluation board and a cable with a connector connects with it. Connector Socket Figure 23. DB-9 connector and socket The table below shows the typical connector pin-out definition. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 40 The S32R27X CSI2 interface supports up to 4 physical data lanes with a maximum data rate of 1Gb/s, and the S32R37X CSI2 interface supports up to 2 physical data lanes with the same overall maximum data rate of 1Gb/s. An example connection is shown in Figure 24 S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 41 D-PHY External resistor connection - 15 kΩ (1% or lower) CSI2_CLKP B7 Input D-PHY Positive D-Phy differential clock line Receiver input CSI2_CLK Input D-PHY Negative D-Phy differential clock line Receiver input Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 42 MIPI CSI2 signals and the low-speed control signals. It also provides ample ground connections to ensure signal integrity. Connector should be placed as close to the S32R device as possible to minimize trace length. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 43 Texas Instruments is used as the ethernet physical transceiver (PHY). This will be used throughout this section to show an example interface. 12. Actual throughput is greater than 100 Mbit/s but significantly less than 1000 Mbit/s S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 44 PD[2], PI[2] ENET_RXD0 Receive Data 0 PD[5] ENET_RXD1 Receive Data 1 PD[6] ENET_RXD2 Receive Data 2 PH[4] ENET_RXD3 Receive Data 3 PH[5] ENET_RXCLK Receive Clock PD[1], PH[13] ENET_RXER Receive Error PH[8] S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 45 Micrel KSZ9031RNX Gigabit Ethernet transceiver with RGMII support. 13. Actual throughput is greater than 100 Mbit/s but significantly less than 1000 Mbit/s. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 46 MagJack RJ45 connector with integrated magnetics is also shown. Care should be taken when routing the high speed signal wires for the transmit and receive differential pairs. See section for details. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 47 Input pin for selecting alternative boot modes. Please see the Boot Assist Module (BAM) and System Status and Configuration Module (SSCM) chapters in the device reference manual for more information. Table continues on the next page... S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 48: High Speed Layout Considerations

    Eliminate vias if at all possible. If vias must be used, make sure they are used across all lanes. • Use the following steps to reduce crosstalk in either microstrip or stripline layouts: S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...

  • Page 49: Revision History

    SD_R requirement. • In MIPI CSI2 interface added updates to show S32R37 considerations and package connections. • Added Table 35 to show all variants pads for each recommendation. S32R27/37 Hardware Design Guide, Rev. 1, 04/2018 NXP Semiconductors...
  • Page 50 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based nxp.com on the information in this document.

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