32 x 12/14 bit 50/75 msps adc for mtca.4 rear-i/o (95 pages)
Summary of Contents for Tews Technologies TPMC371-10
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TPMC371 Conduction Cooled 8 Channel Serial Interface RS232/RS422 Version 1.1 User Manual Issue 1.1.5 January 2009 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone: +49-(0)4101-4058-0 9190 Double Diamond Parkway, Phone: +1 (775) 850 5830 25469 Halstenbek, Germany Fax: +49-(0)4101-4058-19...
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TPMC371-12 in this document at any time without notice. Conduction cooled 4 Channel Serial RS232 TEWS TECHNOLOGIES GmbH is not liable for any (2x full modem), 4 Channel Serial RS422, damage arising out of the application or use of the P14 I/O device described herein.
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Issue Description Date Initial Issue July 2004 Update to Version 1.1 November 2004 Updated Power Specifications & Expanded Configuration EEPROM data Configuration EEPROM data & Pinout clarification October 2005 Channel numbering clarification August 2006 New address TEWS LLC September 2006 1.1.5 New notation for HW Engineering Documentation Releases January 2009...
All modules offer P14 I/O. Each RS232 channel supports RxD, TxD, RTS, CTS and GND. Each RS422 channel supports RxD+/-, TxD+/- and GND. Two channels of the TPMC371-10/-12 offer full modem support (TxD, RxD, CTS, RTS, DSR, DTR, CD, RI and GND) for RS232. Two channels of the TPMC371-11 support RxD+/-, TxD+/-, RTS+/-, CTS+/- and GND for RS422.
I/O Connector PMC P14 I/O (64 pin Mezzanine Connector) Physical Data Power Requirements TPMC371-10: 50 mA typical @ +5V DC (no load) TPMC371-11: 70 mA typical @ +5V DC (no load) TPMC371-12: 60 mA typical @ +5V DC (no load) Operating -40°C to +85°C...
3 Local Space Addressing 3.1 XR17D158 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the XR17D158 local space. XR17D158 PCI Base Size Port Endian Description Address Space Width Mode (Byte) Mapping (Offset in PCI (Bit) Configuration...
3.2.1 UART Register Sets The Device Configuration Space provides a register set for each of the 8 UARTs. UART Register Set Register Set Offset Serial Channel 0 0x0000 Serial Channel 1 0x0200 Serial Channel 2 0x0400 Serial Channel 3 0x0600 Serial Channel 4 0x0800 Serial Channel 5...
3.2.2 Device Configuration Registers The Device Configuration Registers control general operating conditions and monitor the status of various functions. This includes a 16 bit general purpose counter, multipurpose input/outputs (not supported by the TPMC371), sleep mode, soft-reset and device identification, and revision. They are embedded inside the UART 0 Register Set.
3.2.3 UART Channel Configuration Registers Each UART channel has its own set of internal UART configuration registers for its own operation control and status reporting. The following table provides the register offsets within a register set, access types and access control: Register Comment Register...
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The address for a UART Channel Configuration Register x in a UART Register Set for channel y PCI Base Address 0 (PCI Base Address for the UART Register Space) + UART Register Set Offset for channel y + Register Offset for register x Addressing example: The address for the LCR register of UART channel 5 is: PCI Base Address...
0x2E 0x1498 0x03 Subsystem ID 0x2C s.b. Table 4-2 : Configuration EEPROM TPMC371-xx Subsystem ID Value (Offset 0x0C): TPMC371-10 0x000A TPMC371-11 0x000B TPMC371-12 0x000C The words following the configuration data contain: • The module version and revision • The UART clock frequency in Hz •...
5 Configuration Hints The following chart shows the UART interface mapping of the different variants of the TPMC371. TPMC371-10 TPMC371-11 TPMC371-12 RS232 RS422 RS232 RS422 RS232 RS422 UART0 UART1 UART2 UART3 UART4 UART5 UART6 UART7 Table 5-1 : UART interface mapping Other configurations are available as factory build option on a per channel base.
6 Programming Hints 6.1 UART Baud Rate Programming Each of the 8 UART channels of the TPMC371 provides a programmable Baud Rate Generator. The clock of the XR17D158 UART can be divided by any divisor from 1 to 2 – 1. The divisor can be programmed by the UART channel DLM (Divisor MSB) and DLL (Divisor LSB) registers.
These steps should be used to modify the DLM, DLL registers of an UART channel: 1. Write 0x80 to the LCR register of the UART channel (enable access to the DLM, DLL registers). 2. Program the DLM, DLL registers of the UART channel. 3.
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