Download Print this page

Yamaha n8 Service Manual page 36

Digital mixing studio
Hide thumbs Also See for n8:

Advertisement

n8/n12
1394AV-LINK (X6893A00) DICE II
PIN
OUTER
NAME
I/O
NO.
NO.
1
A1
VSS3OP
2
A2
SRAM_WE
O
3
A3
I/O
GPIO4/SRAM_READY
4
A4
I2C_CLK
I/O
5
A5
UART0_TX
O
6
A6
TRST
I
7
A7
TDI
I
8
A8
SCMO
I
9
A9
RESET
I
10
A10
TCB[6]
O
11
A11
TCA[6]
O
12
A12
VDD3OP
13
A13
VSS3I
14
A14
VDD3OP
15
A15
TCB[1]
O
16
A16
TCA[0]
O
17
A17
REFI
I
18
A18
I2S_RX0_D3
I
19
A19
I2S_RX0_BICK
O
20
A20
I2S_RX0_MCK
O
21
B1
D0
I/O
22
B2
SRAM_BS[1]
O
23
B3
SRAM_BS[0]
O
24
B4
CS0
O
25
B5
UART1_RX
I
26
B6
VDD1IH
27
B7
TDO
O
28
B8
TMS
I
29
B9
PLLE
I
30
B10
VDD3OP
31
B11
TCA[5]
O
32
B12
TCB[4]
O
33
B13
TCB[3]
O
34
B14
TCB[2]
O
35
B15
TCA[1]
O
36
B16
FS32
O
37
B17
I2S_RX0_D0
I
38
B18
I2S_RX0_LRCK
O
39
B19
I2S_TX0_D3
O
40
B20
I2S_TX0_D1
O
41
C1
D5
I/O
42
C2
D1
I/O
43
C3
SRAM_OE
O
44
C4
I/O
CS3/EN4_B/GPIO6
45
C5
I2C_DATA
I/O
46
C6
UART1_TX
O
47
C7
VSS3I
48
C8
TCK
I
49
C9
NLIG
I
50
C10
TCA[7]
O
51
C11
TCB[5]
O
52
C12
TCA[4]
O
53
C13
TCA[3]
O
54
C14
TCA[2]
O
55
C15
TCB[0]
O
56
C16
REFO
O
57
C17
I2S_RX0_D1
I
58
C18
I2S_TX0_D2
O
59
C19
I2S_TX0_D0
O
60
C20
I/O
GPIO7/ I2S_TX0_MCK
61
D1
D6
I/O
62
D2
D2
I/O
63
D3
D3
I/O
64
D4
VSS3OP
65
D5
I/O
CS2/EN4_A/GPIO5
66
D6
VDD3OP
67
D7
UART0_RX
I
68
D8
VSS3OP
36
FUNCTION
I/O ground
SRAM write enable
General purpose I/O / SRAM ready (read enable)
I2C Clock
Serial output
JTAG - Test reset (active low)
JTAG - Test data in
Scan mode select
Reset - active low
Test pin
Test pin
I/O 3.3V
Core ground
I/O 3.3V
Test pin
I2S Receiver 0 Data (ch.6/7)
I2S Receiver 0 Bit clock
I2S Receiver 0 Master clock
Data bus
SRAM upper byte select
SRAM lower byte select
Chip select
Serial intput
Core 1.8V
JTAG - Test data out
JTAG - Test mode select
PLL enable
I/O 3.3V
Test pin
I2S Receiver 0 Data (ch.0/1)
I2S Receiver 0 Left/Right clock
I2S Transmitter 0 Data ch.6/7
I2S Transmitter 0 Data ch.2/3
Data bus
SRAM output enable
Chip select / Rotary encoder input / General purpose I/O
I2C Data
Serial output
Core ground
JTAG - Test clock
Ignore PLL no-lock before releasing reset, active high.
Test pin
I2S Receiver 0 Data (ch.2/3)
I2S Transmitter 0 Data ch.4/5
I2S Transmitter 0 Data ch.0/1
General purpose I/O / I2S Transmitter 0 Master clock
Data bus
I/O ground
Chip select / Rotary encoder input / General purpose I/O
I/O 3.3V
Serial intput
I/O ground
PIN
OUTER
NAME
I/O
NO.
NO.
69
D9
TEMO
I
70
D10
TCB[7]
O
71
D11
VDD3OP
72
D12
VDD1IH
73
D13
VSS3OP
74
D14
VDD3OP
75
D15
VDD3OP
76
D16
I2S_RX0_D2
I
77
D17
VSS3OP
78
D18
I/O
GPIO9/ I2S_TX0_LRCLK
79
D19
VDD1IH
80
D20
I2S_RX1_D1
I
81
E1
D9
I/O
82
E2
D8
I/O
83
E3
D7
I/O
84
E4
D4
I/O
85
E17
I/O
GPIO8/I2S_TX0_BICK
86
E18
VSS3I
87
E19
I2S_RX1_D0
I
88
E20
I2S_RX1_MCK
O
89
F1
D13
I/O
90
F2
D12
I/O
91
F3
D10
I/O
92
F4
VDD3OP
93
F17
VDD3OP
94
F18
I2S_RX1_LRCK
O
95
F19
I2S_TX1_D1
O
96
F20
I2S_TX1_LRCLK
O
97
G1
VSS3I
98
G2
D15
I/O
99
G3
D14
I/O
100
G4
D11
I/O
101
G17
I2S_RX1_BICK
O
102
G18
I2S_TX1_D0
O
103
G19
I2S_TX1_BICK
O
104
G20
I2S_TX1_MCK
O
105
H1
A1
O
106
H2
A0
O
107
H3
VDD1IH
108
H4
VSS3OP
109
H17
VSS3OP
110
H18
I2S_RX2_D1
I
111
H19
I2S_RX2_D0
I
112
H20
I2S_RX2_LRCK
O
113
J1
A5
O
114
J2
A4
O
115
J3
A3
O
116
J4
A2
O
117
J9
VSS3OP
118
J10
VSS3OP
119
J11
VSS3OP
120
J12
VSS3OP
121
J17
I2S_RX2_BICK
O
122
J18
I2S_RX2_MCK
O
123
J19
I2S_TX2_D1
O
124
J20
I2S_TX2_D0
O
125
K1
A8
O
126
K2
A6
O
127
K3
A7
O
128
K4
VDD3OP
129
K9
VSS3OP
130
K10
VSS3OP
131
K11
VSS3OP
132
K12
VSS3OP
133
K17
I/O
GPIO12/I2S_TX2_LRCLK
134
K18
I/O
GPIO11/I2S_TX2_BICK
135
K19
I/O
GPIO10/I2S_TX2_MCK
136
K20
HPX1
O
MLAN: IC106
FUNCTION
Test mode pin
Test pin
I/O 3.3V
Core 1.8V
I/O ground
I/O 3.3V
I2S Receiver 0 Data (ch.4/5)
I/O ground
General purpose I/O / I2S Transmitter 0 Left/Right clock
Core 1.8V
I2S Receiver 1 Data (ch.2/3)
Data bus
General purpose I/O / I2S Transmitter 0 Bit clock
Core ground
I2S Receiver 1 Data (ch.0/1)
I2S Receiver 1 Master clock
Data bus
I/O 3.3V
I2S Receiver 1 Left/Right clock
I2S Transmitter 1 Data ch.2/3
I2S Transmitter 1 Left/Right clock
Core ground
Data bus
I2S Receiver 1 Bit clock
I2S Transmitter 1 Data ch.0/1
I2S Transmitter 1 Bit clock
I2S Transmitter 1 Master clock
Address bus
Core 1.8V
I/O ground
I2S Receiver 2 Data (ch.2/3)
I2S Receiver 2 Data (ch.0/1)
I2S Receiver 2 Left/Right clock
Address bus
I/O ground
I2S Receiver 2 Bit clock
I2S Receiver 2 Master clock
I2S Transmitter 2 Data ch.2/3
I2S Transmitter 2 Data ch.0/1
Address bus
I/O 3.3V
I/O ground
General purpose I/O / I2S Transmitter 2 Left/Right clock
General purpose I/O / I2S Transmitter 2 Bit clock
General purpose I/O / I2S Transmitter 2 Master clock
GPIO(Z)

Hide quick links:

Advertisement

Chapters

loading

This manual is also suitable for:

N12