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NXP Semiconductors MC92602 User Manual

NXP Semiconductors MC92602 User Manual

Reduced interface serdes design verification board
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MC92602
Reduced Interface SerDes
Design Verification Board
User's Guide
MC92602DVBUG
Rev. 3, 06/2005

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  • Page 1 MC92602 Reduced Interface SerDes Design Verification Board User’s Guide MC92602DVBUG Rev. 3, 06/2005...

  • Page 3: Table Of Contents

    Parallel Inputs ......................2-6 2.5.1.2 Parallel Outputs ....................... 2-7 2.5.2 and Ground (GND) Access Connections............2-7 2.5.3 Serial Inputs and Outputs..................... 2-7 Special Test Connection....................2-7 Test Traces ........................2-8 MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 4 Transmitter Parallel Data Input Connectors ............... A-3 Output: 2 × 20 (0.100") Connectors................. A-4 TEST_0 Connector ......................A-5 Appendix B Parts List Design Verification Board Parts List ................B-1 MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 5 Paragraph Page Number Title Number Appendix C Prescaler for Jitter Measurement Divide-by-xx Prescaler Description .................C-1 Prescaler Components......................C-2 Appendix D Revision History MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 6 MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 7: General Information

    (DVB) facilitates the full evaluation of the MC92602 Quad Reduced Interface SerDes. It should be read in conjunction with the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide. This design verification board is intended for evaluation and testing purposes only. Freescale does not guarantee its performance in a production environment.

  • Page 8: Specifications

    Low logic level (nominally 0.0 V) BIST Built-in self-test Design verification board Interface No connection Pseudo-noise PRBS Pseudo random bit sequence Test access port Time delay reflectometry UIp-p Peak-to-peak unit interval MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 9: Related Documentation

    U4: Level shift and clock buffer Contact Information For questions concerning the MC92602 design verification kit or to place an order for a kit, contact your local Freescale field applications engineer. MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3...
  • Page 10 CLK_A_PG HSTL_VREF CLK_B_PG R22V2 PG11 PG13 PG10 Ω Horizontal 50- 2×10, 0.100" Connectors TST3 TST7 TST4 TST8 Test Traces Figure 1-1. MC92602 Design Verification Board Block Diagram MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 11: Hardware Preparation And Installation

    2.0 amps from the +5.0-V supply. Actual current consumption depends on the user set voltage levels, clock frequencies, and the MC92602 operating mode. The board contains two +5.0-V connection posts and two ground connection posts. These duplicate connections simplify using a four-wire supply: supply and ground, force and sense.

  • Page 12: Setting The Voltage Regulators

    This supply can be varied over the range +3.3 V ± 0.3 V using the R12V potentiometer. The +1.8-V supply is used to power the MC92602 core logic, transceivers, and on-chip phase-locked loop (PLL). This regulator can be adjusted over the range +1.8 V ± 0.15 V using R22V.

  • Page 13: Hstl Voltage Reference Regulator

    Note that these regulators should be set to voltage limits within the operating ranges described in the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide. Failure to operate within these ranges could cause damage to the MC92602.

  • Page 14: Using The Onboard Oscillator

    SW1 switch 4, be activated, then deactivated after changing the divide-by-xx switch. This will ensure proper frequency generation. Between the MC100ES6222 output and the MC92602 reference clock inputs, REF_CLK_P and REF_CLK_N, is an MC100ES8111 which performs a PECL to HSTL level shift. It also drives two SMA connectors, 1.5V_CLK_OUT5 and 1.5V_CLK_OUT6, with HSTL level clock signals.

  • Page 15: V_Clk_Outn Sma Connectors

    2.4.5 Clock Frequency Selection To accommodate the fact that the MC92602 can receive data on both edges of the reference clock (DDR), of which many pieces of test equipment are single-edge triggered (SDR), the MC92602DVB clock outputs can be programmed to be either the same as the supplied frequency or half the supplied frequency by setting SW1, switches 3, 5, and 6 to either ‘on’...

  • Page 16: Interface Components

    The MC92602 parallel I/O is supplied by the +1.5-V (HSTL) V voltage regulator (set for 1.5 or 1.8 V) and has a rail-to-rail signal swing. There are no bi-directional signals on the MC92602 or on the design verification board. 2.5.1.1 Parallel Inputs The parallel inputs, both data and control, are accessible via 2 ×...

  • Page 17: Parallel Outputs

    2 × 20, 0.100" output connector numbering scheme, with pin 1 labeled on the board. The parallel output signals of the MC92602 are 1.5- or 1.8-V HSTL compatible depending on the setting of the V regulator. A complete mapping of the MC92602 outputs to the 2 × 20, 0.100" connectors is listed in Appendix A, “Connector...

  • Page 18: Test Traces

    The MCS92602DVB design verification board has both vertical and horizontal 50-Ω test traces: • Vertical: TST1–TST5 and TST2–TST6 • Horizontal: TST3–TST7 and TST4–TST8 These traces can be used to determine the impedance of the board using TDR measurement techniques. MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 19: Laboratory Equipment And Quick Setup Evaluation

    The quick setup evaluation procedures outlined below describe how the MC92602DVB can be used to evaluate the data ‘eye diagram’ and a simple error rate test using the internal test features of the MC92602 with a minimal amount of test equipment. Only a power supply and sampling oscilloscope are required.

  • Page 20: Quick Setup Data-Eye Diagram

    • SMA female to SMA female adapters • SMA male to SMA male adapters In-depth testing of the MC92602 can be performed using a bit error rate tester and a jitter analysis system. Table 3-3 provides a listing of test equipment that can be used for these types of tests.

  • Page 21: Quick Setup Data-Eye Generation And Observation

    3.2.1 Quick Setup Data-Eye Generation and Observation A transmitted data-eye can be observed at any of the serial outputs of the MC92602 using its integrated, 23rd order, pseudo-noise (PN) pattern generator. The implementation of the 23-bit PN generator uses the following polynomial.

  • Page 22: Parallel Input Connections

    XMIT_C_3 CTRL_SIG_2 BSYNC +1.5 V XMIT_C_K +1.5 V DROP_SYNC XCVR_C_DISABLE TST_1 C_XCLK XMIT_C_CLK TST_0 +1.5 V D_XMIT0 XMIT_D_0 XMIT_D_1 XMIT_D_2 XMIT_D_3 XMIT_D_K +1.5 V XCVR_D_DISABLE D_XCLK XMITD_CLK MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 23: Basic Eye Observation-Test Procedure

    Table 3-4. This will place the MC92602 in PN generation mode with the MC92602 in reset. Step 2 and 3 may be skipped if previously performed when setting up the DVB. 2. Apply +5.0 V to the evaluation board. Verify voltage levels of +3.3 V, +1.8 V, and +V (1.5 V)

  • Page 24: Quick Setup Bit Error Rate Checking

    Quick Setup Bit Error Rate Checking In addition to having an integrated PN generator, the MC92602 also has a bit error rate checker (BERC). An integrated 23rd order signature analyzer, that is synchronized to the incoming PN stream is used to count code group mismatch errors relative to the internal PN reference pattern.

  • Page 25: Parallel I/O Connections

    This releases the RESET signal. 5. Observe the parallel outputs on the data analyzer. As described in the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide, the MC92602 will start and lock the PLL, initialize the receivers, perform byte alignment, and reset the bit error counter.
  • Page 26 If the receiver counter fills with errors, all bits of RECV_x_[4:0] stay a logic high (11111111) until the receiver is reset. Refer to the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide for more detail.

  • Page 27: Test Setups

    This chapter outlines the laboratory test equipment setup and procedure to evaluate the features of the MC92602 in more depth than those outlined in the previous chapter. These setups are meant to be guidelines only and are not implied to be complete. Details of testing in specific system applications are left to the user.

  • Page 28: Test Setup For Full-Speed Mode

    Test Setups 4.1.1 Test Setup for Full-Speed Mode Figure 4-1 depicts the test setup for MC92602 in full-speed mode (HSE = ‘0’). The control bits are set as follows: • REPE = ‘1’ • TBIE = ‘1’ All other control bits are set to ‘0,’ except RESET, which is initially set to ‘0,’ then transitioned to ‘1’ to start the MC92602.

  • Page 29: Jitter Testing

    Test Setups Jitter Testing The following tests are guidelines for verifying the performance of the MC92602 in ‘noisy’ conditions. Results will vary depending on input reference frequencies, MC92602 mode of operation, test setup and equipment, and test environment. 4.2.1 Jitter Test System Calibration...

  • Page 30: Reference Clock Jitter Transfer Test

    1.25 GHz 125 MHz (Carrier Frequency) Parallel Data 10101 01010 10101 01010 10101 — — — — — — Figure 4-4. Reference Clock Jitter Transfer Test Setup MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 31: Reference Clock Jitter Tolerance Test

    The MC92602 is placed in ten-bit interface mode (TBIE) and repeater mode (REPE). The serial data stream can be set to either PRBS or user-defined data. The control bits are set as follows: •...

  • Page 32: Data Jitter Tolerance Test

    4-6, is used to observe the amount of jitter placed on the serial data inputs that does not produce errors on the serial data outputs. The MC92602 is placed in ten-bit interface mode (TBIE) and repeater mode (REPE). The serial data stream can be set to either PRBS or user-defined data.

  • Page 33: Appendix A Connector Signals

    All the connection test points use the common 2 row 0.100" spaced 3-M type connectors. Input: 2 × 10 (0.100") Connectors The configuration, control, data, and test inputs to the MC92602 are via 2 row by 10 connectors. There are a total of 12 input connectors on the DVB.
  • Page 34 BSYNC Byte synchronization mode DROP_SYNC Drop synchronization TST_1 Test mode—select 1 TST_0 Test mode—select 0 — — — — — — — — — — Ground connection MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 35: Transmitter Parallel Data Input Connectors

    Connector Signals A.1.2 Transmitter Parallel Data Input Connectors The MC92602 transmitter parallel data input signals for channels A through D are mapped to the 2 × 10 connectors as listed in the tables below. Table A-4 shows the 4-bit data (DDR) input for transmitter channels A through D, respectively, on A_XMIT0 to D_XMIT0 (PG8, PG10, PG6, and PG4) connectors.

  • Page 36: Output: 2 × 20 (0.100") Connectors

    RECV_x_RCLK, is brought out to two connector pins. Care should be exercised when connecting to both these pins not to exceed the drive capacity of the chip output. Refer to the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide, for more details.

  • Page 37: Test_0 Connector

    It is important to use a shorting jumper on the TRST input to comply with the above note. For more information on the test access port, see Section 5.1 in the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide, for more details.
  • Page 38 Connector Signals MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...

  • Page 39: Appendix B Parts List

    7 pole DIP slide switches, 2 position (open or closed), surface mount 2 × 8 keyed header with PG12, PG14 2516-6002UB shroud, 0.1" pin spacing, low profile MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 40 68 Ω Newark 68-Ω chip resistor, size 0805 120 Ω Dale CRCW08051200JT 120-Ω chip resistor, size 0805 100 Ω R17, R64 Dale CRCW08051000FT-X 100-Ω chip resistor, size 0805 MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 41 10 KΩ chip resistor, R58, R78–R83 size 0805 50 Ω R2, R7–R9, R57, 50-Ω chip resistor, R65, size 0805 R85–R87 12 Ω 12-Ω chip resistor, size 0805 MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 42 Parts List MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 43 2 × 5 × 4 = 40 Clock In 2 × 10 × 2 = 40 Clock In Schematics for this prescaler are available from your Freescale field applications engineer. MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 44 12-GHz divide-by-2 prescaler, GaAs HBT MMIC. HMC364S8G Hittite Microwave Hittite 12-GHz divide-by-2 prescaler, GaAs HBT MMIC. Pin-for-pin alternative to above part. HMC394LP4 Hittite Microwave Hittite 2.2-GHz programmable 5-bit counter, GaAs HBT MMIC. MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 45 Appendix D Revision History This appendix provides a list of the major differences between revisions of the MC92602 Reduced Interface SerDes Design Verification Board User’s Guide (MC92602DVBUG). Table D-1 provides a revision history for this document. Table D-1. MC92602DVB Revision History Rev.
  • Page 46 Revision History MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3 Freescale Semiconductor...
  • Page 47 BackCover...
  • Page 48 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Information in this document is provided solely to enable system and software Technical Information Center implementers to use Freescale Semiconductor products.

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