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5.3.9 Ethernet
Ethernet interface is compatible with a MII PHY interface from 802.3 - 2008 or a RGMII PHY interface
Ethernet interface is compatible with a MII PHY interface from 802.3
from HP/Marvell specification version 2.6.
from HP/Marvell specification version 2.6.
5.3.10 Audio interfaces
FC7100 module provides digital audio interface only.
FC7100 module provides digital audio interface
The digital audio inter face of the FC7100 is composed of 16 pads, that can be configured in various
face of the FC7100 is composed of 16 pads, that can be configured in various
face of the FC7100 is composed of 16 pads, that can be configured in various
combination, allowing the use of interfaces I2S input and output, TDM inputs and outputs, PCM
combination, allowing the use of interfaces I2S input and output, TDM inputs and outputs, PCM
combination, allowing the use of interfaces I2S input and output, TDM inputs and outputs, PCM
inputs and outputs, SPDIF inputs and outputs, The configuration cannot exceed the fol lowing:
inputs and outputs, SPDIF inputs and outputs, The configuration cannot exceed the fol
inputs and outputs, SPDIF inputs and outputs, The configuration cannot exceed the fol
•
I2S inputs: 8 Stereo (4 of them can be configured as SPDIF
I2S inputs: 8 Stereo (4 of them can be configured as SPDIF -audio)
•
I2S outputs: 4 Stereo
•
TDM inputs: 1 Quad or 1 Octo
TDM inputs: 1 Quad or 1 Octo
•
TDM outputs: 1 Quad or 1 Octo
TDM outputs: 1 Quad or 1 Octo
•
PCM inputs/outputs: 2
•
SPDIF inputs: 1 binary input (+ the 4 SPDIF/audio mentioned above)
SPDIF inputs: 1 binary input (+ the 4 SPDIF/audio mentioned above)
•
SPDIF outpu ts: 1 binary output
ts: 1 binary output
Providing a complete I2S interface (bit clock, left/right clock & master clock), FC7100 operates as
Providing a complete I2S interface (bit clock, left/right clock & master clock), FC7100 operates as
Providing a complete I2S interface (bit clock, left/right clock & master clock), FC7100 operates as
master of the bus for an external audio codec on motherboard.
master of the bus for an external audio codec on motherboard.
If needed, FC7100 I2S interface can be set as slave if the motherboard p
If needed, FC7100 I2S interface can be set as slave if the motherboard provides the needed clock
signals: master clock & Left/Right clock.
signals: master clock & Left/Right clock.
Note: If FC7100 is configured as slave, all the I2S I/O will be synchronized on the motherboard clock.
Note: If FC7100 is configured as slave, all the I2S I/O will be synchronized on the motherboard clock.
Note: If FC7100 is configured as slave, all the I2S I/O will be synchronized on the motherboard clock.
If another I2S master interface must be connected to FC7100, the FC7100 can synchroni
If another I2S master interface must be connected to FC7100, the FC7100 can synchroni
If another I2S master interface must be connected to FC7100, the FC7100 can synchroni ze the I2S
data with the left/right clock.
5.3.11 Video interfaces
FC7100 features input & output video flow management,
FC7100 features input & output video flow management,
5.3.11.1 Display interfaces
FC7100 has two display interfaces:
FC7100 has two display interfaces:
•
LCD_1:
o 24 bits, ITU_656 & ITU_601, 1080p,
24 bits, ITU_656 & ITU_601, 1080p,
o 16 or 8 bits, ITU_656 & ITU_601
16 or 8 bits, ITU_656 & ITU_601
o 3,3V signalling
synchronization signals and can also be used with Data Enable signal only,
synchronization signals and can also be used with Data Enable signal only,
synchronization signals and can also be used with Data Enable signal only,
•
LCD_0: 8 bits, ITU_656 & ITU_601, 720p
LCD_0: 8 bits, ITU_656 & ITU_601, 720p multiplexed with CAM_0,
5.3.11.2 Record interfaces
FC7100 has three record interfaces
FC7100 has three record interfaces :
•
CAM_0:
8 bits, ITU_656 & ITU_601, 720p
8 bits, ITU_656 & ITU_601, 720p
targeting LCD Panel use: It includes Horizontal & Vertical
targeting LCD Panel use: It includes Horizontal & Vertical
Confidential Information
Ref: OEM-2012-149
2008 or a RGMII PHY interface
rovides the needed clock
28/39
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