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[JTAG & Other Connector]
It is prepared an EPLD (Electrically Programmable Logic Device) XC9536XL in case of JP7, for a
program to call Serial Flash and FPGA use it in case of JP10.
It set up a program mode of FPGA in case of JP8. Each program mode setup is as follows.
M2
M1
0
1
1
0
1
*
1. When connect jumper, it is '0'.
*
2. A signal HSWAP_EN has an internal pull-up resistor. When connect jumper, it is '0.
If it is "0', an I/O pin is pull up during configuration period.
A JP13 is connected to switch which it connects in parallel with EPLD. A user uses it when it test
a special function to a manual. (Refer to Schematic)
M0
0
0
Master Serial
1
1
Slave Serial
1
0
Master Parallel
1
1
Slave Parallel
0
1
JTAG
VCC(+3.3V)
TCK
TDI
N.C.
N.C.
HSWAP_EN
MODE 0
MODE 1
MODE 2
SWITCH 2
SWITCH 3
SWITCH 1
SWITCH 5
Configuration Mode
JP7/JP10
GND
1
2
TDO
3
4
TMS
5
6
N.C.
7
8
N.C.
9
10
JP8
GND
1
2
GND
3
4
GND
5
6
GND
7
8
JP13
GND
1
2
GND
3
4
GND
5
6
GND
7
8
21-
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PCI-EK01 Users Manual (Rev 1.0)
http://www.daqsystem.com
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