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CHAPTER 2
PROGRAMMING SPECIFICATIONS
2.0
INTRODUCTION
2.1
PROGRAMMING SPECIFICATIONS
This section defines the Control and Status Registers and the memory data structures required to pro-
gram the LANCE Ethernet Protocol Controller.
2.2 PROGRAMMING THE LANCE
The LANCE is designed to operate in an environment that includes close coupling with a local memory
and a microprocessor (HOST). The LANCE is programmed by a combination of registers and data struc-
tures resident within the LANCE and in memory. There are four Control and Status Registers (CSR's)
within the LANCE which are programmed by the HOST device. Once enabled, the LANCE has the abili-
ty to access external buffer memory locations to acquire additional operating parameters. LANCE has
the ability to do independent buffer management as well as transfer data packets to and from an Ethernet.
There are three memory structures accessed by LANCE, as follows:
1. Initialization Block - 12 words in contiguous memory starting on a word boundary. The initialization
block is assembled by the HOST, and is accessed
r.
LANCE. The initialization block contains the
operating parameters necessary for device operation. I ne initialization block is comprised of:
1. Mode of Operation (1 Word)
2. Physical Address (3 Words)
3. Logical Address Mask (4 Words)
4. Location of Receive and Transmit Descriptor Rings (2 Words)
5. Number of Entries in Receive and Transmit Descriptor Rings (2 Words)
2. Receive and Transmit Descriptor Rings - Two ring structures, one each for incoming and outgoing
packets. Each entry in the rings is 4 words long. Each entry must start on a quadword boundary. The
Descriptor Rings are comprised of:
1. The address of a data buffer.
2. The length of that buffer.
3. Status information associated with the buffer.
3. Data Buffers - Contiguous portions of memory reserved for packet buffering. Data buffers may begin
on arbitrary byte boundaries.
In general, the programming sequence of LANCE may be summarized as:
1. Programming the LANCE CSR's by a HOST device to locate an initialization block in memory.
2. LANCE loading itself with the information contained within the initialization block.
3. LANCE accessing the Descriptor Rings for packet handling.
2.3
CONTROL AND STATUS REGISTERS
There are four Control and Status Registers (CSR's) resident within LANCE. The CSR's are accessed
through two bus addressable ports, an address port (RAP), and a data port (RDP).
2.3.1
ACCESSING THE CONTROL AND STATUS REGISTERS
The CSR's are read (or written) in a two step operation. The address of the CSR is written into
1-113
.
2·1
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