Signal Processor Block Diagram - Sony DVP-F25 Service Manual

3-3. SIGNAL PROCESSOR BLOCK DIAGRAM

MB-106 BOARD (2/5)
(SEE PAGE 4-15 to 4-20)
q;
IC301 <zzz (CL301)
(DVD PLAY)
65 – 74
MA 0 – 9
40ns/div
1.3Vp-p
RF/SERVO
SIG0 111 RFIN1
(SEE PAGE 3-4)
113 RFIN2
qa IC301 <zzc (CL302)
(CD PLAY)
0.2µs/div 1.4Vp-p
9
IC301 <zb/
5.2Vp-p
29.5nsec
26 XINT
XARPIT
27 XCS
XARPCS
28 XWAT
XWAIT
33MARP 150 CLKIN
XWRH 24 XWR
25 XRD
XRD
TRST
HA 0 – 21 HA 0 – 21
SYSTEM CONTROL
(SEE PAGE 3-7)
HD 0 – 15 HD 0 – 15
XRST
512FSAVD
XAVDCS2
XAVDCS3
27MAVD
XAVDIT
DREQ0
DACK0
DREQ1
DACK1
16
IC405
16M SDRAM
IC303
16M DRAM
36 – 43 29 31
(CEK,EC2,HK,SP)
46 – 53 30
MD 0 – 15
77
SD 0 – 7 ı
SDI 0 – 7
84
SDCK
57 SDCK, XSHD,
XSHD
ı
XSRQ, XSAK, SDEF
XSRQ
59
XSAK
63
SDEF 64
IC301
(2/2)
CDDATA, CDBCK,
ARP
169
DATA CDLRCK, CDDOUT
170
BCLK
175
LRCK
DOUT 56
2
A 0 – 7 ı HA 0 – 7
9
134
ı
D 0 – 7 HD 8 – 15
141
TDO 175
TCK 174
TDI 173
TMS 172
TRST 171
LAND
(FOR J TAG)
3-5
IC404
16M SDRAM
ADDT 0 – 15
ADAD 0 – 11
135-138 140-143
105-108 110-113
145-148 150
115 116 118 120
151 153 154
121
SDDQ 0 – 15
qg
IC403 tl
37
ı
40
H
DTI 0 – 7
42
ı
45
qh
IC403 ya
ICLKI
IERRI
47
ı ISTARTI
51
IVALI
H
IREQO
31
CDIN2I
qk IC403 yg
32
CDIN1I
34
CDBCKI
35
CDLRKI
1.2Vp-p
H
168-169
171-174
176-179
HA 0 – 21 HAD 0 – 21
181-184
qd
IC403 tg
186-189
191-194
2 – 5
930mVp-p
H
7 – 10
HD 0 – 15 HD 0 – 15
12 – 15
17 – 20
IC403
97 TDI
AV DECODER
99 TCK
98 TDO
101 TMS
102 TRST
XRD
196 HCSn
XWRH
197 HRWn
qs
IC403 ws
207 RSTn
5.0Vp-p
22 ACLK 40.8nsec
ql
166 HAD23 IC403 <zb, <zn/
167 HAD22
158 CLKI
5.3Vp-p
37nsec
160 SCLKI
200 HWAIT0n
HIREQ0
199
202 – 205
122 124 125
127 129 130
132 133
qf
IC403 tj
930mVp-p
H
Y/G
G OUT 57
660mVp-p
CB/R
R OUT 59
CR/B
B OUT 61
COMPOUT
COMPOUT 65
660mVp-p
YOUT
Y OUT 55
COUT
C OUT 63
qj
IC403 yd
920mVp-p
H
VREFI 70
RV402
VIDEO
LEVEL
ADJ
ACH12 24
ACH34 25
LAND
ACH56 26
LRCKO 28
BCKO 29
DO 30
3-6
DVP-F25
CN604 (1/4)
4 Y-OUT
Cb-OUT
9
8 Cr-OUT
VIDEO
(SEE PAGE 3-9)
12 VIDEO OUT
6 S/Y-OUT
1 S/C-OUT
ACH12
AUDIO
LRCK
(SEE PAGE 3-11)
BCK
SPDIF1