Silicon Laboratories Si8281-EVB User Manual page 5

VIN
VIN
GNDA
VDDA
J11
VDDA
1
JP2
R6
10K
D4
VDDA
D11 C7
FLT 10uF
R8 R9
10K 10K
J6
1
RST
J7
1
FLT
J8
1
RDY
J9
1
IN+
J10
1
IN-
S1
RST
+IN/-IN have weak internal pull down
(4uA).
Signal sources should be placed as close
as possilbe to +IN/-IN inputs to minimize
noise coupling.
+IN and - IN should be terminated directly
to VDDA/GNDA accordingly if not used.
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1. DC/DC is built to drive to create +15/-11V.
2. To operate with positive voltage gate drive only:
VIN
C1 10uF
TP8
VSW
JS2
U1
1
GNDP
2
VSW
3
VDDP
4
VDDA
5
GNDA
6
C18 C8 C9
RST
10uF 0.1uF 0.1uF
7
FLT
8
RDY
9
IN+
10
IN-
Si8281CD-IS
R28 R29
10K 10K
Figure 2.2. Si8281 Circuit Schematic
a. Remove R13
b. Install R14 = 0 Ohm
c. Change divider VDDB-VSSB = (R1/R2 +1) x 1.05V
TP9
T1_SEC8
4 8
D1 B160
3
C2
100pF
6
R13 0
7
2
R5
100
1 5
B160 D2
T1
2.5uH
T1_SEC5
TP10
TP13
VSNS
20
VSNS
19
R3 200K
COMP
18
NC
17
DSAT
16
VDDB
15
VH
VH
14 VL
VL
13
CLMP
CLMP
12
VMID
11
R14
VSSB
0
NI
Prototyping area
2 4 6 8 10 121416
J4
1 3 5 7 9 11 1315
NI
2 4 6 8 10 121416
J5
1 3 5 7 9 111315
NI
Resistor value and power rating for R10, R11,
R12 are dependent on switching frequency and
gate loading of the IGBT/MOSFET device.
UG167: Si8281-EVB User's Guide
VPWR
VDDB
VDDB
R7
10K
D5
VDDB
VDDB
VSSB
C3 C4
10uF 0.1uF
TP11
VMID/GNDB
1
VMID
C5 C6
10uF 0.1uF
VSSB
VDDB
R1
182K
R2
7.87K
C10 1.5nF
VSSB VSSB
R4 100 D10
VDDB
JP1 JS1
C13 C12 C16
0.1uF 10uF 390pF
VMID
C15 C14
0.1uF 10uF
VSSB
TO-220 pinout place holder
DSAT
TPV13
GATE
VH D9 NI R27 NI
GATE
R10 25
VL R11 10
R12 1.0
TPV12
CLMP
VMID
CLMP
DSAT
GATE GATE
C17 C11
NI NI
VMID VMID
Discrete Capacitor Load TO- 247 pinout place holder
Schematics
VPWR
VDDB
VMID
VSSB
ES1F DSAT
VPWR
Q2
NI
VPWR
Q1
NI
Rev. 0.1 | 4