Silicon Laboratories C8051F064-EK User Manual page 12

C8051F064-EK
9.7. External Memory Interface (J11, J14)
The C8051F064 evaluation board provides an External Memory Interface by connecting a 128 kB SRAM to the
device port pins. The device's External Memory Interface can be enabled by installing a shorting block at header
J11. This connects port pin P4.5 to the Chip Select (CS) signal on the SRAM, pulling this signal low. Placing a
shorting block on header J14, Pin 2 and Pin 3, enables the use of the lower address bank on the SRAM. Moving
the shorting block to J14, Pin 1 and Pin 2, enables port pin P3.7 to select between the upper and lower address
banks on the SRAM. Refer to Table 4 for the external memory interface signal descriptions.
Table 4. External Memory Interface Signal Descriptions
9.8. PORT I/O Connectors (J15)
The Port 0 signals on the C8051F064 have their own 10-pin header (J15). This header provides a pin for each of
the corresponding port pins 0-7, +3.3 V and digital ground. See Table 5 for the J15 pin connections.
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SRAM Signal C8051F060 Signal
WE P4.7
CS P4.5 (J11)
OE P4.6
V +3VD2
DD
GND GND
I/O0...I/O7 P7.0...P7.7
A0...A7 P6.0...P6.7
A8...A15 P5.0...P5.7
A16 P3.7 (J14[1-2])
A16 GND (J14[2-3])
Table 5. J15 Port Connector Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
Description
Write Enable
Chip Select
Output Enable
Digital Power
Digital Ground
Data Bus
Address Bus Low Byte
Address Bus High Byte
Bank Select
Bank Select Always 0
Description
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
+3 VD (+3.3 V)
GND (Ground)
Rev. 0.4