Xilinx I2S Product Manual page 20

Channel 2/3 Control (0x34)
The IP provides a mechanism to route the audio from any I2S input. For example, audio received
on I2S Channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one
I2S channel can be routed to all of the 8 audio channels.
Table 22: Receiver Channel 2/3 Control (0x34)
Default
Bit
Value
31:3
2:0 0x2
Channel 4/5 Control (0x38)
The IP provides a mechanism to route the audio from any I2S input. For example, audio received
on I2S Channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one
I2S channel can be routed to all of the 8 audio channels.
Table 23: Receiver Channel 4/5 Control (0x38)
Default
Bit
Value
31:3
2:0 0x3
Channel 6/7 Control (0x3C)
The IP provides a mechanism to route the audio from any I2S input. For example, audio received
on I2S Channel 0 can be routed to any of the 8 audio channels. Similarly audio received on one
I2S channel can be routed to all of the eight audio channels.
PG308 (v1.0) April 4, 2018
I2S Transmitter and I2S Receiver
Access
Type
Reserved
R/W Channel Mux Value: Specify a value to Multiplex the audio channel output.
0x0 : disabled
0x1 : Audio received on I2S channel 1 is routed as audio channel 0 /1
0x2 : Audio received on I2S channel 1 is routed as audio channel 2 /3
0x3 : Audio received on I2S channel 1 is routed as audio channel 4 /5
0x4: Audio received on I2S channel 1 is routed as audio channel 6 /7
Any other value are reserved
Access
Type
Reserved
R/W Channel Mux Value: Specify a value to Multiplex the audio channel output.
0x0 : disabled
0x1 : Audio received on I2S channel 2 is routed as audio channel 0 /1
0x2 : Audio received on I2S channel 2 is routed as audio channel 2 /3
0x3 : Audio received on I2S channel 2 is routed as audio channel 4 /5
0x4: Audio received on I2S channel 2 is routed as audio channel 6 /7
Any other value are reserved
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Chapter 3: Product Specification
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