Xilinx I2S Product Manual page 13

Control Register (0x08)
This register provides capability to enable/disable the core.
Table 5: Transmitter Control Register (0×08)
Default
Bit
Value
31:1 0
0 0x0
Interrupt Control Register (0x10)
This registers determines the interrupts sources in the Interrupt Status register that are allowed
to generate an interrupt. Writing a '1' to a bit will enable the corresponding interrupt.
Table 6: Transmitter Interrupt Control Register (0×10)
Default
Bit
Value
31 0
30:4
3 0
2 0
1 0
0 0
Interrupt Status (0x14)
This register returns the status of the Interrupt bits.
Table 7: Transmitter Interrupt Status (0×14)
Default
Bit
Value
31:4
3 0
2 0
1 0
PG308 (v1.0) April 4, 2018
I2S Transmitter and I2S Receiver
Access
Type
RO Reserved
R/W Enable: Setting this bit to '1' will enable the core operations. Setting this bit to '0'
disables the core operations
Access
Type
R/W Global Interrupt Enable: Enable Global Interrupt
Reserved
R/W Underflow Interrupt Enable: Enable Underflow Interrupt
R/W AES Channel Status Updated Interrupt enable: Enable AES Channel Status
Updated Interrupt
R/W AES Block Sync Error Interrupt enable: Enable AES block sync interrupt
R/W AES Block Completed Interrupt enable: Enable AES Block Completed interrupt
Access
Type
Reserved
R/W Underflow Interrupt: This bit is set when the core did not receive the samples for
all channels in time. This scenario can lead to distortions in the audio that is
being played. Write a '1' to clear this bit.
R/W AES Channel Status Updated: This bit is set when a change in captured AES
channel status has been detected. Write a '1' to clear this flag.
R/W AES Block Sync Error: This bit is set when synchronization with the start of an AES
block has been lost. This occurs if the incoming audio our AXIS does violates the
guidelines. Write a '1' to clear this flag.
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Chapter 3: Product Specification
Description
Description
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