Xilinx I2S Product Manual page 18

Table 16: Receiver Core Configuration (0x04) (cont'd)
Default
Bit
Value
7:1
0
Control Register (0x08)
This register provides capability to enable/disable the core.
Table 17: Receiver Control Register (0×08)
Default
Bit
Value
31:17 0
16 0
15:1
0 0x0
Interrupt Control Register (0x10)
This registers determines the interrupts sources in the Interrupt Status register that are allowed
to generate an interrupt. Writing a '1' to a bit enables the corresponding interrupt.
Table 18: Receiver Interrupt Control Register (0×10)
Default
Bit
Value
31 0
30:2
1 0
0 0
Interrupt Status (0x14)
This register returns the status of the Interrupt bits.
PG308 (v1.0) April 4, 2018
I2S Transmitter and I2S Receiver
Access
Type
RSVD
RO Is I2S Master: Indicates if the core has been generated as an I2S Master or Slave.
1 = I2S Master
Access
Type
R Reserved
R/W Latch AES Channel Status: Program this bit to latch the AES Channel Status bits
from registers. This latched value is then put onto the AXIS interface. This
register is auto cleared.
Reserved
R/W Enable: Setting this bit to '1' enables the core operations. Setting this bit to '0'
disables the core operations
Access
Type
R/W Global Interrupt Enable: Enable Global Interrupt
Reserved
R/W Overflow Interrupt Enable: Enable overflow interrupt
R/W AES Block Completed Interrupt enable: Enable AES Block Completed interrupt
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Chapter 3: Product Specification
Description
Description
Description
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