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Connector Specifications
FPGA
Pin #
G5
F5
B1
C2
D2
M14
L15
R11
P12
3.7.2
Software Access
Software access to each of the interface signals available through the IO Expansion
Connector is described below.
3.7.2.1
IO Configurable via the FPGA
The on-board Altera
the 80-pin IO Expansion Connector. An FPGA sample configuration file is provided
Pin Name
FPGA_ADC_1
FPGA_ADC_2
FPGA_ADC_3
GND
AERO_RTF_DRONE_VBATS
ENSE / FPGA_ADC_4
FPGA_ADC_5
GND
CPU_GPIO_05
CPU_GPIO_06
GND
CPU_GPIO_01
CPU_HSUART0_TX
CPU_HSUART0_RX
GND
CPU_GPIO_02
CPU_GPIO_03
GND
CPU_GPIO_04
CPU_GPIO_07
GND
FPGA_GPIO_21
FPGA_GPIO_22
GND
FPGA_GPIO_23
FPGA_GPIO_24
FC_CAN_L
FC_CAN_H
GND
RESERVED
RESERVED
GND
RESERVED
RESERVED
GND
RESERVED
®
MAX
®
10 FPGA allows user-configurable IO that are routed to
Pin#
Pin#
AERO_RTF_FC_SDIO /
11
12
AERO_RTF_FC_SDIO /
13
14
AERO_RTF_FC_SDIO /
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
11
FPGA
Pin Name
Pin #
M4
FGPA_GPIO_26
R3
FGPA_GPIO_27
P3
FGPA_GPIO_28
GND
FPGA_GPIO_01
P15
FPGA_GPIO_02
R14
FPGA_GPIO_03
M9
FPGA_GPIO_04
L9
GND
FPGA_GPIO_05
N1
FPGA_GPIO_06
P2
FPGA_GPIO_07
L4
FPGA_GPIO_08
L5
GND
FPGA_GPIO_09
K4
FPGA_GPIO_10
K5
FPGA_GPIO_11
J4
FPGA_GPIO_12
B13
GND
FPGA_GPIO_13
A14
FPGA_GPIO_14
D12
FPGA_GPIO_15
A5
FPGA_GPIO_16
C8
GND
FPGA_GPIO_17
E9
FPGA_GPIO_18
E11
FPGA_GPIO_19
P1
FPGA_GPIO_20
R2
GND
CPU_CAN_H
CPU_CAN_L
GND
+VBAT
+VBAT
RESERVED
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