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Symbol
Pin
Number
S_OCLK
31
S_DEN
30
S_PSYNC
28
S_UNCOR
27
SADDR[1:0]
10,11
SDA
8
SCL
6
TEST
12
ENSERI
13
TRST
14
TDO
20
TCK
18
TDI
17
Circuit- and IC description
Type
DESCRIPTION
T
demodulation, de-interleaving, RS decoding and de-scrambling.
4mA
In serial mode. This output can be set to tri-state (default state at reset).
I/O
Serial Output CLock. S_OCLK is the output clock for the serial S_DO
T
output. S_OCLK is internally generated depending on which interface is
4mA
selected.
This output can be set to tri-state (default state at reset).
I/O
Serial Data Enable : this output signal is high when there is a valid data
T
on output bus S_DO.
4mA
This output can be set to tri-state (default state at reset).
I/O
Serial TS Pulse SYNChro. This output signal goes high when the sync
T
byte (47
) is provided, then it goes low until the next sync byte.
16
4mA
S_PSYNC is high during the first bit of the sync byte (47
bit of the sync byte depending on I2C programming
This output can be set to tri-state (default state at reset).
I/O
Serial TS UNCORrectable packet. This output signal is high when the
T
provided packet is uncorrectable (during the 188 bytes of the packet).
4mA
The uncorrectable packet is not affected by the Reed Solomon decoder,
but the MSB of the byte following the sync byte is forced «1 » for the
MPEG2 process: Error Flag Indicator (if RSI and IEI are set low in the I2C
table).
This output can be set to tri-state (default state at reset).
I
SADDR are the 2 LSBs of the I2C address of the TDA10046A.
(5v tol)
The MSBs are internally set to 00010. Therefore the complete I2C
address of the TDA10046A is (MSB to LSB) : 0,0,0,0,1,0, SADDR[1],
SADDR[0].
I/O
I2C data input. SDA is a bi-directional signal. It is the serial input/output of
(5v tol)
the I2C internal block. A pull-up resistor (typically 4.7 kΩ) must be
4mA
connected between SDA and VDD for proper operation (Open Drain
output).
I
I2C clock input. SCL should nominally be a square wave with a maximum
(5v tol)
frequency of 400KHz. SCL is generated by the system I2C master.
I
Test input pin. For normal operation of the TDA10046A, TEST must be
(5v tol)
grounded.
I
When high this pin enables the serial output transport stream through the
(5v tol)
boundary scan pins (TRST,TDO,TCK,TDI,TMS).
Must be set low in boundary scan mode.
I/O
Test ReSeT. This active low input signal is used to reset the TAP
T
controller when in boundary scan mode.
(5v tol)
In normal mode of operation TRST must be set low.
4mA
In serial mode, TRST is the uncorrectable output (S_UNCOR)
O
Test Data Out. This is the serial Test output pin used in boundary scan
T
mode. Serial Data are provided on the falling edge of TCK.
(5v tol)
In Serial mode, TDO is the data output (S_DO).
4mA
I/O
Test ClocK : an independent clock used to drive the TAP controller when
T
in boundary scan mode. In normal mode of operation, TCK must be set
(5v tol)
low.
4mA
In serial mode, TCK is the clock output (S_OCLK).
I/O
Test Data In. The serial input for Test data and instruction when in
T
boundary scan mode. In normal mode of operation, TDI must be set to
3139 785 31681
) or during the 8
16
9.
EN 235
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