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PIN DESCRIPTION AND CONFIGURATION
Pin
Input/Output
Pin Name
1
I
DGND
2
I
MCLK
3
I
CLATCH
4
I
CCLK
5
I
CDATA
6
NC
7
I
192/
8
O
ZEROR
9
I
DEEMP
10
I
96/
11, 15
I
AGND
12
O
OUTR+
13
O
OUTR–
14
O
FILTR
16
O
OUTL–
17
O
OUTL+
18
I
AVDD
19
FILTB
20
I
IDPM1
21
I
IDPM0
22
O
ZEROL
23
I
MUTE
24
I
25
I
L/ CLK
26
I
BCLK
27
I
SDATA
28
I
DVDD
Table I. Serial Data Input Mode
IDPM1 (Pin 20) IDPM0 (Pin 21)
0
0
0
1
1
0
1
1
Circuit- and IC description
Description
Digital Ground.
Master Clock Input. Connect to an external clock source at either 256 F
512 F
, 768 F
, or 1024 F
S
S
Latch Input for Control Data. This input is rising-edge sensitive.
Control Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used
for specifying channel-specific attenuation and mute.
No Connect.
Selects 48 kHz (LO) or 192 kHz Sample Frequency.
Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used
to impose a 50 μs/15 μs response characteristic on the output audio spectrum at an
assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.
Selects 48 kHz (LO) or 96 kHz Sample Frequency.
Analog Ground.
Right Channel Positive Line Level Analog Output.
Right Channel Negative Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10 μF and 0.1 μF capacitors to the AGND.
Left Channel Negative Line Level Analog Output.
Left Channel Positive Line Level Analog Output.
Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection. Connect 10 μF capacitor to AGND (Pin 15).
Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port
registers are reset to the default values. Connect HI for normal operation.
Left/
Clock Input for Input Data. Must run continuously.
Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a
burst fashion.
Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos
complement data per channel.
Digital Power Supply Connect to digital 5 V supply.
Serial Data Input Format
Right-Justified
2
I
S-Compatible
Left-Justified
DSP
3139 785 31681
.
S
9.
EN 201
, 384 F
,
S
S
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